diff options
-rw-r--r-- | firmware/SOURCES | 2 | ||||
-rw-r--r-- | firmware/export/as3525.h | 2 | ||||
-rw-r--r-- | firmware/export/s3c2440.h | 2 | ||||
-rw-r--r-- | firmware/target/arm/mmu-arm.S | 38 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/mmu-s5l8700.S | 95 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/mmu-target.h | 43 |
6 files changed, 31 insertions, 151 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index 95131ab25b..ac3adacab4 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -1369,7 +1369,7 @@ target/arm/tcc780x/cowond2/audio-cowond2.c | |||
1369 | 1369 | ||
1370 | #ifdef CPU_S5L870X | 1370 | #ifdef CPU_S5L870X |
1371 | target/arm/s5l8700/system-s5l8700.c | 1371 | target/arm/s5l8700/system-s5l8700.c |
1372 | target/arm/s5l8700/mmu-s5l8700.S | 1372 | target/arm/mmu-arm.S |
1373 | #ifndef SIMULATOR | 1373 | #ifndef SIMULATOR |
1374 | #ifndef BOOTLOADER | 1374 | #ifndef BOOTLOADER |
1375 | target/arm/s5l8700/timer-s5l8700.c | 1375 | target/arm/s5l8700/timer-s5l8700.c |
diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h index 4a9ab5f40e..358b0c4c93 100644 --- a/firmware/export/as3525.h +++ b/firmware/export/as3525.h | |||
@@ -20,6 +20,8 @@ | |||
20 | #ifndef __AS3525_H__ | 20 | #ifndef __AS3525_H__ |
21 | #define __AS3525_H__ | 21 | #define __AS3525_H__ |
22 | 22 | ||
23 | #define CACHEALIGN_BITS (5) | ||
24 | |||
23 | #define UART_CHANNELS 1 | 25 | #define UART_CHANNELS 1 |
24 | 26 | ||
25 | 27 | ||
diff --git a/firmware/export/s3c2440.h b/firmware/export/s3c2440.h index da2ea8937f..d2de6d25c8 100644 --- a/firmware/export/s3c2440.h +++ b/firmware/export/s3c2440.h | |||
@@ -21,6 +21,8 @@ | |||
21 | #ifndef __S3C2440_H__ | 21 | #ifndef __S3C2440_H__ |
22 | #define __S3C2440_H__ | 22 | #define __S3C2440_H__ |
23 | 23 | ||
24 | #define CACHEALIGN_BITS (5) | ||
25 | |||
24 | #define LCD_BUFFER_SIZE (320*240*2) | 26 | #define LCD_BUFFER_SIZE (320*240*2) |
25 | #define TTB_SIZE (0x4000) | 27 | #define TTB_SIZE (0x4000) |
26 | /* must be 16Kb (0x4000) aligned */ | 28 | /* must be 16Kb (0x4000) aligned */ |
diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S index 947e96b75e..0119b26133 100644 --- a/firmware/target/arm/mmu-arm.S +++ b/firmware/target/arm/mmu-arm.S | |||
@@ -22,7 +22,6 @@ | |||
22 | #include "cpu.h" | 22 | #include "cpu.h" |
23 | 23 | ||
24 | /* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */ | 24 | /* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */ |
25 | /* WARNING : assume size of a data cache line == 32 bytes */ | ||
26 | 25 | ||
27 | #if CONFIG_CPU == TCC7801 || CONFIG_CPU == AT91SAM9260 | 26 | #if CONFIG_CPU == TCC7801 || CONFIG_CPU == AT91SAM9260 |
28 | /* MMU present but unused */ | 27 | /* MMU present but unused */ |
@@ -40,19 +39,38 @@ | |||
40 | #define USE_MMU | 39 | #define USE_MMU |
41 | #define CACHE_SIZE 16 | 40 | #define CACHE_SIZE 16 |
42 | 41 | ||
42 | #elif CONFIG_CPU == S5L8701 | ||
43 | /* MMU not present */ | ||
44 | #define CACHE_SIZE 4 | ||
45 | |||
43 | #else | 46 | #else |
44 | #error Cache settings unknown for this CPU ! | 47 | #error Cache settings unknown for this CPU ! |
45 | 48 | ||
46 | #endif /* CPU specific configuration */ | 49 | #endif /* CPU specific configuration */ |
47 | 50 | ||
48 | @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ | 51 | @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ |
49 | @ assume 64-way set associative separate I/D caches, 32B (2^5) cache line size | 52 | @ assume 64-way set associative separate I/D caches |
50 | @ CACHE_SIZE = N (kB) = N*2^10 B | 53 | @ CACHE_SIZE = N (kB) = N*2^10 B |
51 | @ number of lines = N*2^(10-5) = N*2^(5) | 54 | @ number of lines = N*2^(10-CACHEALIGN_BITS) |
52 | @ Index bits = 6 | 55 | @ Index bits = 6 |
53 | @ Segment loops = N*2^(5-6) = N*2^(-1) = N/2 | 56 | @ Segment loops = N*2^(10-CACHEALIGN_BITS-6) = N*2^(4-CACHEALIGN_BITS) |
57 | @ Segment loops = N/2^(CACHEALIGN_BITS - 4) | ||
58 | @ Segment loops = N/(1<<(CACHEALIGN_BITS - 4)) | ||
59 | |||
60 | #ifdef CACHE_SIZE | ||
54 | 61 | ||
62 | #if CACHEALIGN_BITS == 4 | ||
63 | #define INDEX_STEPS CACHE_SIZE | ||
64 | #elif CACHEALIGN_BITS == 5 | ||
55 | #define INDEX_STEPS (CACHE_SIZE/2) | 65 | #define INDEX_STEPS (CACHE_SIZE/2) |
66 | #endif /* CACHEALIGN_BITS */ | ||
67 | |||
68 | @ assume 64-way set associative separate I/D caches (log2(64) == 6) | ||
69 | @ Index format: 31:26 = index, M:N = segment, remainder = SBZ | ||
70 | @ Segment bits = log2(cache size in bytes / cache line size in byte) - Index bits (== 6) | ||
71 | @ N = CACHEALIGN_BITS | ||
72 | |||
73 | #endif /* CACHE_SIZE */ | ||
56 | 74 | ||
57 | 75 | ||
58 | #ifdef USE_MMU | 76 | #ifdef USE_MMU |
@@ -318,15 +336,13 @@ cpucache_flush: | |||
318 | bne clean_dcache | 336 | bne clean_dcache |
319 | mov r1, #0 | 337 | mov r1, #0 |
320 | #else | 338 | #else |
321 | @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ, assume 64-way set associative separate I/D caches | ||
322 | @ N = log2(cache size in bytes / cache line size in bytes == 32) - 6 /* index bits */ + 4 /* start offset */ | ||
323 | mov r1, #0x00000000 @ | 339 | mov r1, #0x00000000 @ |
324 | 1: @ clean_start @ | 340 | 1: @ clean_start @ |
325 | mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index | 341 | mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index |
326 | add r0, r1, #0x00000020 @ | 342 | add r0, r1, #(1<<CACHEALIGN_BITS) |
327 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | 343 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index |
328 | .rept INDEX_STEPS - 2 /* 2 steps already executed */ | 344 | .rept INDEX_STEPS - 2 /* 2 steps already executed */ |
329 | add r0, r0, #0x00000020 @ | 345 | add r0, r0, #(1<<CACHEALIGN_BITS) |
330 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | 346 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index |
331 | .endr | 347 | .endr |
332 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | 348 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end |
@@ -351,15 +367,13 @@ invalidate_dcache: | |||
351 | bne invalidate_dcache | 367 | bne invalidate_dcache |
352 | mov r1, #0 | 368 | mov r1, #0 |
353 | #else | 369 | #else |
354 | @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ, assume 64-way set associative separate I/D caches | ||
355 | @ N = log2(cache size in bytes / cache line size in bytes == 32) - 6 /* index bits */ + 4 /* start offset */ | ||
356 | mov r1, #0x00000000 @ | 370 | mov r1, #0x00000000 @ |
357 | 1: @ inv_start @ | 371 | 1: @ inv_start @ |
358 | mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index | 372 | mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index |
359 | add r0, r1, #0x00000020 @ | 373 | add r0, r1, #(1<<CACHEALIGN_BITS) |
360 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | 374 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index |
361 | .rept INDEX_STEPS - 2 /* 2 steps already executed */ | 375 | .rept INDEX_STEPS - 2 /* 2 steps already executed */ |
362 | add r0, r0, #0x00000020 @ | 376 | add r0, r0, #(1<<CACHEALIGN_BITS) |
363 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | 377 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index |
364 | .endr | 378 | .endr |
365 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | 379 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end |
diff --git a/firmware/target/arm/s5l8700/mmu-s5l8700.S b/firmware/target/arm/s5l8700/mmu-s5l8700.S deleted file mode 100644 index 35406b9c5c..0000000000 --- a/firmware/target/arm/s5l8700/mmu-s5l8700.S +++ /dev/null | |||
@@ -1,95 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006,2007 by Greg White | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "cpu.h" | ||
23 | |||
24 | /** Cache coherency **/ | ||
25 | |||
26 | /* | ||
27 | * Cleans entire DCache | ||
28 | * void clean_dcache(void); | ||
29 | */ | ||
30 | .section .icode, "ax", %progbits | ||
31 | .align 2 | ||
32 | .global clean_dcache | ||
33 | .type clean_dcache, %function | ||
34 | .global cpucache_flush @ Alias | ||
35 | clean_dcache: | ||
36 | cpucache_flush: | ||
37 | @ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ | ||
38 | mov r1, #0x00000000 @ | ||
39 | 1: @ clean_start @ | ||
40 | mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index | ||
41 | add r0, r1, #0x00000010 @ | ||
42 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | ||
43 | add r0, r0, #0x00000010 @ | ||
44 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | ||
45 | add r0, r0, #0x00000010 @ | ||
46 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | ||
47 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | ||
48 | bne 1b @ clean_start @ | ||
49 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | ||
50 | bx lr @ | ||
51 | .size clean_dcache, .-clean_dcache | ||
52 | |||
53 | /* | ||
54 | * Invalidate entire DCache | ||
55 | * will do writeback | ||
56 | * void invalidate_dcache(void); | ||
57 | */ | ||
58 | .section .icode, "ax", %progbits | ||
59 | .align 2 | ||
60 | .global invalidate_dcache | ||
61 | .type invalidate_dcache, %function | ||
62 | invalidate_dcache: | ||
63 | @ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ | ||
64 | mov r1, #0x00000000 @ | ||
65 | 1: @ inv_start @ | ||
66 | mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index | ||
67 | add r0, r1, #0x00000010 @ | ||
68 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | ||
69 | add r0, r0, #0x00000010 @ | ||
70 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | ||
71 | add r0, r0, #0x00000010 @ | ||
72 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | ||
73 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | ||
74 | bne 1b @ inv_start @ | ||
75 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | ||
76 | bx lr @ | ||
77 | .size invalidate_dcache, .-invalidate_dcache | ||
78 | |||
79 | /* | ||
80 | * Invalidate entire ICache and DCache | ||
81 | * will do writeback | ||
82 | * void invalidate_idcache(void); | ||
83 | */ | ||
84 | .section .icode, "ax", %progbits | ||
85 | .align 2 | ||
86 | .global invalidate_idcache | ||
87 | .type invalidate_idcache, %function | ||
88 | .global cpucache_invalidate @ Alias | ||
89 | invalidate_idcache: | ||
90 | cpucache_invalidate: | ||
91 | mov r2, lr @ save lr to r2, call uses r0 and r1 only | ||
92 | bl invalidate_dcache @ Clean and invalidate entire DCache | ||
93 | mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) | ||
94 | mov pc, r2 @ | ||
95 | .size invalidate_idcache, .-invalidate_idcache | ||
diff --git a/firmware/target/arm/s5l8700/mmu-target.h b/firmware/target/arm/s5l8700/mmu-target.h deleted file mode 100644 index e2515c0df0..0000000000 --- a/firmware/target/arm/s5l8700/mmu-target.h +++ /dev/null | |||
@@ -1,43 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006,2007 by Greg White | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /* This file MUST be included in your system-target.h file if you want arm | ||
23 | * cache coherence functions to be called (I.E. during codec load, etc). | ||
24 | */ | ||
25 | |||
26 | #ifndef MMU_S5L8700_H | ||
27 | #define MMU_S5L8700_H | ||
28 | |||
29 | /* Cleans entire DCache */ | ||
30 | void clean_dcache(void) ICODE_ATTR; | ||
31 | |||
32 | /* Invalidate entire DCache */ | ||
33 | /* will do writeback */ | ||
34 | void invalidate_dcache(void) ICODE_ATTR; | ||
35 | |||
36 | /* Invalidate entire ICache and DCache */ | ||
37 | /* will do writeback */ | ||
38 | void invalidate_idcache(void) ICODE_ATTR; | ||
39 | |||
40 | #define HAVE_CPUCACHE_INVALIDATE | ||
41 | #define HAVE_CPUCACHE_FLUSH | ||
42 | |||
43 | #endif /* MMU_S5L8700_H */ | ||