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-rw-r--r--firmware/export/config/xduoox3.h2
-rw-r--r--firmware/target/mips/ingenic_jz47xx/codec-jz4760.c23
2 files changed, 13 insertions, 12 deletions
diff --git a/firmware/export/config/xduoox3.h b/firmware/export/config/xduoox3.h
index 484e52d151..6cc1aa2e57 100644
--- a/firmware/export/config/xduoox3.h
+++ b/firmware/export/config/xduoox3.h
@@ -106,7 +106,7 @@
106#define HAVE_SW_TONE_CONTROLS 106#define HAVE_SW_TONE_CONTROLS
107 107
108/* define the bitmask of hardware sample rates */ 108/* define the bitmask of hardware sample rates */
109#define HW_SAMPR_CAPS SAMPR_CAP_ALL_96 109#define HW_SAMPR_CAPS SAMPR_CAP_ALL_192
110 110
111#define AB_REPEAT_ENABLE 111#define AB_REPEAT_ENABLE
112 112
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
index 60bfecb08c..b00b3fddef 100644
--- a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
+++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
@@ -208,9 +208,6 @@ void audiohw_set_frequency(int fsel)
208 // bclk is 2,3,4,6,8,12 ONLY 208 // bclk is 2,3,4,6,8,12 ONLY
209 // mclk is 1..512 209 // mclk is 1..512
210 210
211 // for cs4398, BCLK must be 4 for single-rate, 2 for double-rate, 1 for quad-rate!
212
213 // 11.025 and 22.050 are a little wonky.
214 switch(fsel) 211 switch(fsel)
215 { 212 {
216 case HW_FREQ_8: // 0.512 MHz 213 case HW_FREQ_8: // 0.512 MHz
@@ -222,8 +219,6 @@ void audiohw_set_frequency(int fsel)
222 case HW_FREQ_11: // 0.7056 MHz 219 case HW_FREQ_11: // 0.7056 MHz
223 pll1_speed = 508000000 / 3; 220 pll1_speed = 508000000 / 3;
224 mclk_div = 180 / 3; 221 mclk_div = 180 / 3;
225// pll1_speed = 0;
226// mclk_div = 272;
227 bclk_div = 4; 222 bclk_div = 4;
228 func_mode = 0; 223 func_mode = 0;
229 break; 224 break;
@@ -242,8 +237,6 @@ void audiohw_set_frequency(int fsel)
242 case HW_FREQ_22: // 1.4112 MHz 237 case HW_FREQ_22: // 1.4112 MHz
243 pll1_speed = 508000000 / 3; 238 pll1_speed = 508000000 / 3;
244 mclk_div = 90 / 3; 239 mclk_div = 90 / 3;
245// pll1_speed = 0;
246// mclk_div = 136;
247 bclk_div = 4; 240 bclk_div = 4;
248 func_mode = 0; 241 func_mode = 0;
249 break; 242 break;
@@ -263,8 +256,6 @@ void audiohw_set_frequency(int fsel)
263 case HW_FREQ_44: // 2.8224 MHz 256 case HW_FREQ_44: // 2.8224 MHz
264 pll1_speed = 508000000 / 3; 257 pll1_speed = 508000000 / 3;
265 mclk_div = 45 / 3; 258 mclk_div = 45 / 3;
266// pll1_speed = 0;
267// mclk_div = 68;
268 bclk_div = 4; 259 bclk_div = 4;
269 dem = CS4398_DEM_44100; 260 dem = CS4398_DEM_44100;
270 func_mode = 0; 261 func_mode = 0;
@@ -285,8 +276,6 @@ void audiohw_set_frequency(int fsel)
285 case HW_FREQ_88: // 5.6448 MHz 276 case HW_FREQ_88: // 5.6448 MHz
286 pll1_speed = 508000000 / 3; 277 pll1_speed = 508000000 / 3;
287 mclk_div = 45 / 3; 278 mclk_div = 45 / 3;
288// pll1_speed = 0;
289// mclk_div = 68;
290 bclk_div = 2; 279 bclk_div = 2;
291 func_mode = 1; 280 func_mode = 1;
292 break; 281 break;
@@ -296,6 +285,18 @@ void audiohw_set_frequency(int fsel)
296 bclk_div = 2; 285 bclk_div = 2;
297 func_mode = 1; 286 func_mode = 1;
298 break; 287 break;
288 case HW_FREQ_176: // 11.2896 MHz
289 pll1_speed = 508000000*2;
290 mclk_div = 45;
291 bclk_div = 2;
292 func_mode = 2;
293 break;
294 case HW_FREQ_192: // 12.288 MHz
295 pll1_speed = 516000000;
296 mclk_div = 42/2;
297 bclk_div = 2;
298 func_mode = 2;
299 break;
299 default: 300 default:
300 return; 301 return;
301 } 302 }