4 files changed, 10 insertions, 10 deletions

diff --git a/firmware/drivers/tlv320.c b/firmware/drivers/tlv320.c
index bae1f59f95..e2ad5d7594 100644
--- a/firmware/drivers/tlv320.c
+++ b/firmware/drivers/tlv320.c
@@ -81,7 +81,7 @@ void tlv320_init(void)
     tlv320_write_reg(REG_DAIF, DAIF_IWL_16|DAIF_FOR_I2S);
     tlv320_set_headphone_vol(0, 0);
     tlv320_write_reg(REG_DIA, DIA_ACT);
-    tlv320_write_reg(REG_SRC, SRC_CLKIN);
+    tlv320_write_reg(REG_SRC, (8 << 2)); /* 44.1kHz */
 }
 
 /**
diff --git a/firmware/pcm_playback.c b/firmware/pcm_playback.c
index 22dc34d7c2..9e28891e6d 100644
--- a/firmware/pcm_playback.c
+++ b/firmware/pcm_playback.c
@@ -118,20 +118,20 @@ void pcm_set_frequency(unsigned int frequency)
     switch(frequency)
     {
     case 11025:
-        pcm_freq = 0x4;
+        pcm_freq = 0x2;
 #ifdef HAVE_UDA1380
         uda1380_set_nsorder(3);
 #endif
         break;
     case 22050:
-        pcm_freq = 0x6;
+        pcm_freq = 0x4;
 #ifdef HAVE_UDA1380
         uda1380_set_nsorder(3);
 #endif
         break;
     case 44100:
     default:
-        pcm_freq = 0xC;
+        pcm_freq = 0x6;
 #ifdef HAVE_UDA1380
         uda1380_set_nsorder(5);
 #endif
diff --git a/firmware/system.c b/firmware/system.c
index ec7feb7a21..87bec1b2e8 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -600,7 +600,7 @@ void set_cpu_frequency(long frequency)
               /* Refresh timer for bypass frequency */
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
-        PLLCR = 0x11856005;
+        PLLCR = 0x11c56005;
         CSCR0 = 0x00001180; /* Flash: 4 wait states */
         CSCR1 = 0x00000980; /* LCD: 2 wait states */
         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -617,7 +617,7 @@ void set_cpu_frequency(long frequency)
               /* Refresh timer for bypass frequency */
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
-        PLLCR = 0x1385e005;
+        PLLCR = 0x13c5e005;
         CSCR0 = 0x00000580; /* Flash: 1 wait state */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -633,7 +633,7 @@ void set_cpu_frequency(long frequency)
               /* Refresh timer for bypass frequency */
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
-        PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */
+        PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */
         CSCR0 = 0x00000180; /* Flash: 0 wait states */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
         DCR = (0x8000 | DEFAULT_REFRESH_TIMER);       /* Refresh timer */
diff --git a/firmware/target/coldfire/iaudio/x5/system-x5.c b/firmware/target/coldfire/iaudio/x5/system-x5.c
index dee605733f..97d5ecc715 100644
--- a/firmware/target/coldfire/iaudio/x5/system-x5.c
+++ b/firmware/target/coldfire/iaudio/x5/system-x5.c
@@ -37,7 +37,7 @@ void set_cpu_frequency(long frequency)
               /* Refresh timer for bypass frequency */
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
-        PLLCR = 0x13042045;
+        PLLCR = 0x13442045;
         CSCR0 = 0x00001180; /* Flash: 4 wait states */
         CSCR1 = 0x00000980; /* LCD: 2 wait states */
         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -54,7 +54,7 @@ void set_cpu_frequency(long frequency)
               /* Refresh timer for bypass frequency */
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
-        PLLCR = 0x16030045;
+        PLLCR = 0x16430045;
         CSCR0 = 0x00000580; /* Flash: 1 wait state */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -70,7 +70,7 @@ void set_cpu_frequency(long frequency)
               /* Refresh timer for bypass frequency */
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
-        PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */
+        PLLCR = 0x10400200; /* Power down PLL, but keep CLSEL and CRSEL */
         CSCR0 = 0x00000180; /* Flash: 0 wait states */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
         DCR = (0x8000 | DEFAULT_REFRESH_TIMER);       /* Refresh timer */