diff options
-rw-r--r-- | firmware/export/config-gigabeat-s.h | 2 | ||||
-rwxr-xr-x | firmware/export/imx31l.h | 77 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/ata-imx31.c | 39 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/ata-target.h | 23 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/button-imx31.c | 44 |
5 files changed, 119 insertions, 66 deletions
diff --git a/firmware/export/config-gigabeat-s.h b/firmware/export/config-gigabeat-s.h index 30b708ae1d..ae85908994 100644 --- a/firmware/export/config-gigabeat-s.h +++ b/firmware/export/config-gigabeat-s.h | |||
@@ -1,6 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * This config file is for toshiba Gigabeat S | 2 | * This config file is for toshiba Gigabeat S |
3 | */ | 3 | */ |
4 | |||
5 | #define NO_LOW_BATTERY_SHUTDOWN | ||
4 | #define TARGET_TREE /* this target is using the target tree system */ | 6 | #define TARGET_TREE /* this target is using the target tree system */ |
5 | 7 | ||
6 | #define TOSHIBA_GIGABEAT_S 1 | 8 | #define TOSHIBA_GIGABEAT_S 1 |
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index b1f35e80f2..b10fc1ea17 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -25,8 +25,6 @@ | |||
25 | 25 | ||
26 | /* Place in the section with the framebuffer */ | 26 | /* Place in the section with the framebuffer */ |
27 | #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) | 27 | #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) |
28 | #define IRAM_BASE_ADDR 0x1fffc000 | ||
29 | #define L2CC_BASE_ADDR 0x30000000 | ||
30 | 28 | ||
31 | /*Frame Buffer and TTB defines from gigabeat f/x build*/ | 29 | /*Frame Buffer and TTB defines from gigabeat f/x build*/ |
32 | #define FRAME ((short *)0x80100000) /* Framebuffer */ | 30 | #define FRAME ((short *)0x80100000) /* Framebuffer */ |
@@ -37,6 +35,8 @@ | |||
37 | /* | 35 | /* |
38 | * AIPS 1 | 36 | * AIPS 1 |
39 | */ | 37 | */ |
38 | #define IRAM_BASE_ADDR 0x1fffc000 | ||
39 | #define L2CC_BASE_ADDR 0x30000000 | ||
40 | #define AIPS1_BASE_ADDR 0x43F00000 | 40 | #define AIPS1_BASE_ADDR 0x43F00000 |
41 | #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR | 41 | #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR |
42 | #define MAX_BASE_ADDR 0x43F04000 | 42 | #define MAX_BASE_ADDR 0x43F04000 |
@@ -133,15 +133,70 @@ | |||
133 | 133 | ||
134 | 134 | ||
135 | /* ATA */ | 135 | /* ATA */ |
136 | #define TIME_OFF (*(REG8_PTR_T)0x43F8C000) | 136 | #define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00)) |
137 | #define TIME_ON (*(REG8_PTR_T)0x43F8C001) | 137 | #define ATA_TIME_ON (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01)) |
138 | #define TIME_1 (*(REG8_PTR_T)0x43F8C002) | 138 | #define ATA_TIME_1 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02)) |
139 | #define TIME_2W (*(REG8_PTR_T)0x43F8C003) | 139 | #define ATA_TIME_2W (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03)) |
140 | #define TIME_2R (*(REG8_PTR_T)0x43F8C004) | 140 | /* PIO */ |
141 | #define TIME_AX (*(REG8_PTR_T)0x43F8C005) | 141 | #define ATA_TIME_2R (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04)) |
142 | #define TIME_PIO_RDX (*(REG8_PTR_T)0x43F8C00F) | 142 | #define ATA_TIME_AX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05)) |
143 | #define TIME_4 (*(REG8_PTR_T)0x43F8C007) | 143 | #define ATA_TIME_4 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07)) |
144 | #define TIME_9 (*(REG8_PTR_T)0x43F8C008) | 144 | #define ATA_TIME_9 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08)) |
145 | /* MDMA */ | ||
146 | #define ATA_TIME_M (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09)) | ||
147 | #define ATA_TIME_JN (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A)) | ||
148 | #define ATA_TIME_D (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B)) | ||
149 | #define ATA_TIME_K (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C)) | ||
150 | /* UDMA */ | ||
151 | #define ATA_TIME_ACK (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D)) | ||
152 | #define ATA_TIME_ENV (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E)) | ||
153 | #define ATA_TIME_PIO_RDX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F)) | ||
154 | #define ATA_TIME_ZAH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10)) | ||
155 | #define ATA_TIME_MLIX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11)) | ||
156 | #define ATA_TIME_DVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12)) | ||
157 | #define ATA_TIME_DZFS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13)) | ||
158 | #define ATA_TIME_DVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14)) | ||
159 | #define ATA_TIME_CVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15)) | ||
160 | #define ATA_TIME_SS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16)) | ||
161 | #define ATA_TIME_CYC (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17)) | ||
162 | /* */ | ||
163 | #define ATA_FIFO_DATA_32 (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18)) | ||
164 | #define ATA_FIFO_DATA_16 (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c)) | ||
165 | #define ATA_FIFO_FILL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20)) | ||
166 | /* Actually ATA_CONTROL but conflicts arise */ | ||
167 | #define ATA_INTF_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24)) | ||
168 | #define ATA_INTERRUPT_PENDING (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28)) | ||
169 | #define ATA_INTERRUPT_ENABLE (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c)) | ||
170 | #define ATA_INTERRUPT_CLEAR (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30)) | ||
171 | #define ATA_FIFO_ALARM (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34)) | ||
172 | #define ATA_DRIVE_DATA (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0)) | ||
173 | #define ATA_DRIVE_FEATURES (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4)) | ||
174 | #define ATA_DRIVE_SECTOR_COUNT (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8)) | ||
175 | #define ATA_DRIVE_SECTOR_NUM (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC)) | ||
176 | #define ATA_DRIVE_CYL_LOW (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0)) | ||
177 | #define ATA_DRIVE_CYL_HIGH (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4)) | ||
178 | #define ATA_DRIVE_CYL_HEAD (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8)) | ||
179 | #define ATA_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */ | ||
180 | #define ATA_DRIVE_COMMAND (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */ | ||
181 | #define ATA_ALT_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */ | ||
182 | #define ATA_DRIVE_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */ | ||
183 | |||
184 | /* ATA_INTF_CONTROL flags */ | ||
185 | #define ATA_FIFO_RST (1 << 7) | ||
186 | #define ATA_ATA_RST (1 << 6) | ||
187 | #define ATA_FIFO_TX_EN (1 << 5) | ||
188 | #define ATA_FIFO_RCV_EN (1 << 4) | ||
189 | #define ATA_DMA_PENDING (1 << 3) | ||
190 | #define ATA_DMA_ULTRA_SELECTED (1 << 2) | ||
191 | #define ATA_DMA_WRITE (1 << 1) | ||
192 | #define ATA_IORDY_EN (1 << 0) | ||
193 | |||
194 | /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */ | ||
195 | #define ATA_INTRQ1 (1 << 7) | ||
196 | #define ATA_FIFO_UNDERFLOW (1 << 6) | ||
197 | #define ATA_FIFO_OVERFLOW (1 << 5) | ||
198 | #define ATA_CONTROLLER_IDLE (1 << 4) | ||
199 | #define ATA_INTRQ2 (1 << 3) | ||
145 | 200 | ||
146 | /* Timers */ | 201 | /* Timers */ |
147 | #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00)) | 202 | #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00)) |
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c index a61e848594..19e440724a 100644 --- a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c | |||
@@ -26,14 +26,14 @@ | |||
26 | #include "pcf50606.h" | 26 | #include "pcf50606.h" |
27 | #include "ata-target.h" | 27 | #include "ata-target.h" |
28 | 28 | ||
29 | #define ATA_RST (1 << 6) | ||
30 | |||
31 | void ata_reset(void) | 29 | void ata_reset(void) |
32 | { | 30 | { |
33 | ATA_CONTROL &= ~ATA_RST; | 31 | ATA_INTF_CONTROL &= ~ATA_ATA_RST; |
34 | sleep(1); | 32 | sleep(1); |
35 | ATA_CONTROL |= ATA_RST; | 33 | ATA_INTF_CONTROL |= ATA_ATA_RST; |
36 | sleep(1); | 34 | sleep(1); |
35 | |||
36 | while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE)); | ||
37 | } | 37 | } |
38 | 38 | ||
39 | /* This function is called before enabling the USB bus */ | 39 | /* This function is called before enabling the USB bus */ |
@@ -44,7 +44,7 @@ void ata_enable(bool on) | |||
44 | 44 | ||
45 | bool ata_is_coldstart(void) | 45 | bool ata_is_coldstart(void) |
46 | { | 46 | { |
47 | return 0; | 47 | return true; |
48 | } | 48 | } |
49 | 49 | ||
50 | unsigned long get_pll(bool serial) { | 50 | unsigned long get_pll(bool serial) { |
@@ -110,26 +110,27 @@ unsigned long get_ata_clock(void) { | |||
110 | 110 | ||
111 | void ata_device_init(void) | 111 | void ata_device_init(void) |
112 | { | 112 | { |
113 | ATA_CONTROL |= ATA_RST; /* Make sure we're not in reset mode */ | 113 | ATA_INTF_CONTROL |= ATA_ATA_RST; /* Make sure we're not in reset mode */ |
114 | |||
115 | while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE)); | ||
114 | 116 | ||
115 | /* Setup the timing for PIO mode */ | 117 | /* Setup the timing for PIO mode */ |
116 | int T = 1000 * 1000 * 1000 / get_ata_clock(); | 118 | int T = 1000 * 1000 * 1000 / get_ata_clock(); |
117 | TIME_OFF = 3; | 119 | ATA_TIME_OFF = 3; |
118 | TIME_ON = 3; | 120 | ATA_TIME_ON = 3; |
119 | 121 | ||
120 | TIME_1 = (T + 70)/T; | 122 | ATA_TIME_1 = (T + 70)/T; |
121 | TIME_2W = (T + 290)/T; | 123 | ATA_TIME_2W = (T + 290)/T; |
122 | TIME_2R = (T + 290)/T; | 124 | ATA_TIME_2R = (T + 290)/T; |
123 | TIME_AX = (T + 50)/T; | 125 | ATA_TIME_AX = (T + 50)/T; |
124 | TIME_PIO_RDX = 1; | 126 | ATA_TIME_PIO_RDX = 1; |
125 | TIME_4 = (T + 30)/T; | 127 | ATA_TIME_4 = (T + 30)/T; |
126 | TIME_9 = (T + 20)/T; | 128 | ATA_TIME_9 = (T + 20)/T; |
127 | } | 129 | } |
128 | 130 | ||
129 | #if !defined(BOOTLOADER) | 131 | #if !defined(BOOTLOADER) |
130 | void copy_read_sectors(unsigned char* buf, int wordcount) | 132 | void copy_write_sectors(const unsigned char* buf, int wordcount) |
131 | { | 133 | { |
132 | (void)buf; | 134 | (void)buf; (void)wordcount; |
133 | (void)wordcount; | ||
134 | } | 135 | } |
135 | #endif | 136 | #endif |
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-target.h b/firmware/target/arm/imx31/gigabeat-s/ata-target.h index 6dd6da9134..8b37c37d48 100644 --- a/firmware/target/arm/imx31/gigabeat-s/ata-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/ata-target.h | |||
@@ -23,20 +23,19 @@ | |||
23 | #define PREFER_C_READING | 23 | #define PREFER_C_READING |
24 | #define PREFER_C_WRITING | 24 | #define PREFER_C_WRITING |
25 | #if !defined(BOOTLOADER) | 25 | #if !defined(BOOTLOADER) |
26 | #define ATA_OPTIMIZED_READING | 26 | #define ATA_OPTIMIZED_WRITING |
27 | void copy_read_sectors(unsigned char* buf, int wordcount); | 27 | void copy_write_sectors(const unsigned char* buf, int wordcount); |
28 | #endif | 28 | #endif |
29 | 29 | ||
30 | #define ATA_IOBASE 0x43F8C000 | 30 | #define ATA_DATA ATA_DRIVE_DATA |
31 | #define ATA_DATA (*((volatile unsigned short*)(ATA_IOBASE + 0xA0))) | 31 | #define ATA_ERROR ATA_DRIVE_FEATURES |
32 | #define ATA_ERROR (*((volatile unsigned char*)(ATA_IOBASE + 0xA4))) | 32 | #define ATA_NSECTOR ATA_DRIVE_SECTOR_COUNT |
33 | #define ATA_NSECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0xA8))) | 33 | #define ATA_SECTOR ATA_DRIVE_SECTOR_NUM |
34 | #define ATA_SECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0xAC))) | 34 | #define ATA_LCYL ATA_DRIVE_CYL_LOW |
35 | #define ATA_LCYL (*((volatile unsigned char*)(ATA_IOBASE + 0xB0))) | 35 | #define ATA_HCYL ATA_DRIVE_CYL_HIGH |
36 | #define ATA_HCYL (*((volatile unsigned char*)(ATA_IOBASE + 0xB4))) | 36 | #define ATA_SELECT ATA_DRIVE_CYL_HEAD |
37 | #define ATA_SELECT (*((volatile unsigned char*)(ATA_IOBASE + 0xB8))) | 37 | #define ATA_COMMAND ATA_DRIVE_COMMAND |
38 | #define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0xBC))) | 38 | #define ATA_CONTROL ATA_DRIVE_CONTROL |
39 | #define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE + 0xD8))) | ||
40 | 39 | ||
41 | #define STATUS_BSY 0x80 | 40 | #define STATUS_BSY 0x80 |
42 | #define STATUS_RDY 0x40 | 41 | #define STATUS_RDY 0x40 |
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c index 32d2a63c49..eea0faa4eb 100644 --- a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c | |||
@@ -36,31 +36,27 @@ void button_init_device(void) | |||
36 | { | 36 | { |
37 | unsigned int reg_val; | 37 | unsigned int reg_val; |
38 | /* Enable keypad clock */ | 38 | /* Enable keypad clock */ |
39 | //mxc_clks_enable(KPP_CLK); | 39 | CLKCTL_CGR1 |= (3 << 2*10); |
40 | 40 | ||
41 | /* Enable number of rows in keypad (KPCR[7:0]) | 41 | /* Enable number of rows in keypad (KPCR[7:0]) |
42 | * Configure keypad columns as open-drain (KPCR[15:8]) | 42 | * Configure keypad columns as open-drain (KPCR[15:8]) |
43 | * | 43 | * |
44 | * Configure the rows/cols in KPP | 44 | * Configure the rows/cols in KPP |
45 | * LSB nibble in KPP is for 8 rows | 45 | * LSB nibble in KPP is for 8 rows |
46 | * MSB nibble in KPP is for 8 cols | 46 | * MSB nibble in KPP is for 8 cols |
47 | */ | 47 | */ |
48 | reg_val = KPP_KPCR; | 48 | #if 0 |
49 | reg_val |= (1 << 8) - 1; /* LSB */ | 49 | KPP_KPCR = (0xff << 8) | 0xff; |
50 | reg_val |= ((1 << 8) - 1) << 8; /* MSB */ | 50 | /* Write 0's to KPDR[15:8] */ |
51 | KPP_KPCR = reg_val; | 51 | reg_val = KPP_KPDR; |
52 | 52 | reg_val &= 0x00ff; | |
53 | /* Write 0's to KPDR[15:8] */ | 53 | KPP_KPDR = reg_val; |
54 | reg_val = KPP_KPDR; | 54 | |
55 | reg_val &= 0x00ff; | 55 | /* Configure columns as output, rows as input (KDDR[15:0]) */ |
56 | KPP_KPDR = reg_val; | 56 | KPP_KDDR = 0xff00; |
57 | 57 | #endif | |
58 | /* Configure columns as output, rows as input (KDDR[15:0]) */ | 58 | |
59 | KPP_KDDR = 0xff00; | 59 | KPP_KPSR = (1 << 3) | (1 << 2); |
60 | |||
61 | reg_val = 0xD; | ||
62 | reg_val |= (1 << 8); | ||
63 | KPP_KPSR = reg_val; | ||
64 | } | 60 | } |
65 | 61 | ||
66 | inline bool button_hold(void) | 62 | inline bool button_hold(void) |