diff options
-rw-r--r-- | firmware/export/system.h | 29 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/system-target.h | 4 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 2 |
3 files changed, 15 insertions, 20 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h index 7dd01b5c93..9df382bc24 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h | |||
@@ -293,11 +293,13 @@ static inline void cpucache_flush(void) | |||
293 | } | 293 | } |
294 | #endif | 294 | #endif |
295 | 295 | ||
296 | #ifdef PROC_NEEDS_CACHEALIGN | 296 | #ifdef CACHEALIGN_BITS |
297 | /* Cache alignment attributes and sizes are enabled */ | ||
298 | |||
299 | /* 2^CACHEALIGN_BITS = the byte size */ | 297 | /* 2^CACHEALIGN_BITS = the byte size */ |
300 | #define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS) | 298 | #define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS) |
299 | #endif | ||
300 | |||
301 | #ifdef PROC_NEEDS_CACHEALIGN | ||
302 | /* Cache alignment attributes and sizes are enabled */ | ||
301 | 303 | ||
302 | #define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE))) | 304 | #define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE))) |
303 | /* Aligns x up to a CACHEALIGN_SIZE boundary */ | 305 | /* Aligns x up to a CACHEALIGN_SIZE boundary */ |
@@ -312,16 +314,6 @@ static inline void cpucache_flush(void) | |||
312 | /* Aligns a buffer pointer and size to proper boundaries */ | 314 | /* Aligns a buffer pointer and size to proper boundaries */ |
313 | #define CACHEALIGN_BUFFER(start, size) \ | 315 | #define CACHEALIGN_BUFFER(start, size) \ |
314 | ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) | 316 | ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) |
315 | /* Pad a size so the buffer can be aligned later */ | ||
316 | #define CACHE_PAD(x) ((x) + CACHEALIGN_SIZE - 1) | ||
317 | /* Number of bytes in the last cacheline assuming buffer of size x is aligned */ | ||
318 | #define CACHE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1)) | ||
319 | |||
320 | #ifdef NEEDS_STORAGE_ALIGN | ||
321 | #define STORAGE_ALIGN_DOWN(x) CACHEALIGN_DOWN(x) | ||
322 | #define STORAGE_PAD(x) CACHE_PAD(x) | ||
323 | #define STORAGE_OVERLAP(x) CACHE_OVERLAP(x) | ||
324 | #endif | ||
325 | 317 | ||
326 | #else /* ndef PROC_NEEDS_CACHEALIGN */ | 318 | #else /* ndef PROC_NEEDS_CACHEALIGN */ |
327 | 319 | ||
@@ -333,12 +325,17 @@ static inline void cpucache_flush(void) | |||
333 | #define CACHEALIGN_DOWN(x) (x) | 325 | #define CACHEALIGN_DOWN(x) (x) |
334 | /* Make no adjustments */ | 326 | /* Make no adjustments */ |
335 | #define CACHEALIGN_BUFFER(start, size) | 327 | #define CACHEALIGN_BUFFER(start, size) |
336 | #define CACHE_PAD(x) (x) | ||
337 | #define CACHE_OVERLAP(x) 0 | ||
338 | 328 | ||
339 | #endif /* PROC_NEEDS_CACHEALIGN */ | 329 | #endif /* PROC_NEEDS_CACHEALIGN */ |
340 | 330 | ||
341 | #if !defined(PROC_NEEDS_CACHEALIGN) || !defined(NEEDS_STORAGE_ALIGN) | 331 | #ifdef STORAGE_WANTS_ALIGN |
332 | #define STORAGE_ALIGN_DOWN(x) \ | ||
333 | ((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS)) | ||
334 | /* Pad a size so the buffer can be aligned later */ | ||
335 | #define STORAGE_PAD(x) ((x) + CACHEALIGN_SIZE - 1) | ||
336 | /* Number of bytes in the last cacheline assuming buffer of size x is aligned */ | ||
337 | #define STORAGE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1)) | ||
338 | #else | ||
342 | #define STORAGE_ALIGN_DOWN(x) (x) | 339 | #define STORAGE_ALIGN_DOWN(x) (x) |
343 | #define STORAGE_PAD(x) (x) | 340 | #define STORAGE_PAD(x) (x) |
344 | #define STORAGE_OVERLAP(x) 0 | 341 | #define STORAGE_OVERLAP(x) 0 |
diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h index c531344b64..5f91032d9e 100644 --- a/firmware/target/arm/s5l8700/system-target.h +++ b/firmware/target/arm/s5l8700/system-target.h | |||
@@ -29,10 +29,8 @@ | |||
29 | #define CPUFREQ_NORMAL 47923200 | 29 | #define CPUFREQ_NORMAL 47923200 |
30 | #define CPUFREQ_MAX 191692800 | 30 | #define CPUFREQ_MAX 191692800 |
31 | 31 | ||
32 | /* DMA engine needs aligned addresses */ | ||
33 | #define PROC_NEEDS_CACHEALIGN | ||
34 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ | 32 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ |
35 | #define NEEDS_STORAGE_ALIGN | 33 | #define WANTS_STORAGE_ALIGN |
36 | 34 | ||
37 | #define inl(a) (*(volatile unsigned long *) (a)) | 35 | #define inl(a) (*(volatile unsigned long *) (a)) |
38 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) | 36 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) |
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 1422e6467a..157a450743 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -164,7 +164,7 @@ static inline void wake_core(int core) | |||
164 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ | 164 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ |
165 | 165 | ||
166 | #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) | 166 | #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) |
167 | #define NEEDS_STORAGE_ALIGN | 167 | #define STORAGE_WANTS_ALIGN |
168 | #endif | 168 | #endif |
169 | 169 | ||
170 | /** cache functions **/ | 170 | /** cache functions **/ |