diff options
-rw-r--r-- | bootloader/x1000/utils.c | 11 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/boot-x1000.c | 2 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/installer-x1000.c | 4 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.c | 41 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.h | 32 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/spl-nand-x1000.c | 4 |
6 files changed, 47 insertions, 47 deletions
diff --git a/bootloader/x1000/utils.c b/bootloader/x1000/utils.c index 17eb502e1b..46624b0d1d 100644 --- a/bootloader/x1000/utils.c +++ b/bootloader/x1000/utils.c | |||
@@ -146,14 +146,15 @@ int load_uimage_file(const char* filename, | |||
146 | 146 | ||
147 | struct nand_reader_data | 147 | struct nand_reader_data |
148 | { | 148 | { |
149 | nand_drv* ndrv; | 149 | struct nand_drv* ndrv; |
150 | nand_page_t page; | 150 | nand_page_t page; |
151 | nand_page_t end_page; | 151 | nand_page_t end_page; |
152 | unsigned offset; | 152 | unsigned offset; |
153 | uint32_t count; | 153 | uint32_t count; |
154 | }; | 154 | }; |
155 | 155 | ||
156 | static int uimage_nand_reader_init(struct nand_reader_data* d, nand_drv* ndrv, | 156 | static int uimage_nand_reader_init(struct nand_reader_data* d, |
157 | struct nand_drv* ndrv, | ||
157 | uint32_t addr, uint32_t length) | 158 | uint32_t addr, uint32_t length) |
158 | { | 159 | { |
159 | unsigned pg_size = ndrv->chip->page_size; | 160 | unsigned pg_size = ndrv->chip->page_size; |
@@ -177,7 +178,7 @@ static int uimage_nand_reader_init(struct nand_reader_data* d, nand_drv* ndrv, | |||
177 | static ssize_t uimage_nand_reader(void* buf, size_t count, void* rctx) | 178 | static ssize_t uimage_nand_reader(void* buf, size_t count, void* rctx) |
178 | { | 179 | { |
179 | struct nand_reader_data* d = rctx; | 180 | struct nand_reader_data* d = rctx; |
180 | nand_drv* ndrv = d->ndrv; | 181 | struct nand_drv* ndrv = d->ndrv; |
181 | unsigned pg_size = ndrv->chip->page_size; | 182 | unsigned pg_size = ndrv->chip->page_size; |
182 | size_t read_count = 0; | 183 | size_t read_count = 0; |
183 | int rc; | 184 | int rc; |
@@ -223,7 +224,7 @@ static ssize_t uimage_nand_reader(void* buf, size_t count, void* rctx) | |||
223 | int load_uimage_flash(uint32_t addr, uint32_t length, | 224 | int load_uimage_flash(uint32_t addr, uint32_t length, |
224 | struct uimage_header* uh, size_t* sizep) | 225 | struct uimage_header* uh, size_t* sizep) |
225 | { | 226 | { |
226 | nand_drv* ndrv = nand_init(); | 227 | struct nand_drv* ndrv = nand_init(); |
227 | nand_lock(ndrv); | 228 | nand_lock(ndrv); |
228 | if(nand_open(ndrv) != NAND_SUCCESS) { | 229 | if(nand_open(ndrv) != NAND_SUCCESS) { |
229 | splashf(5*HZ, "NAND open failed"); | 230 | splashf(5*HZ, "NAND open failed"); |
@@ -259,7 +260,7 @@ int dump_flash(int fd, uint32_t addr, uint32_t length) | |||
259 | static char buf[8192]; | 260 | static char buf[8192]; |
260 | int ret = 0; | 261 | int ret = 0; |
261 | 262 | ||
262 | nand_drv* ndrv = nand_init(); | 263 | struct nand_drv* ndrv = nand_init(); |
263 | nand_lock(ndrv); | 264 | nand_lock(ndrv); |
264 | 265 | ||
265 | ret = nand_open(ndrv); | 266 | ret = nand_open(ndrv); |
diff --git a/firmware/target/mips/ingenic_x1000/boot-x1000.c b/firmware/target/mips/ingenic_x1000/boot-x1000.c index f59ec5c4ea..2f2714c67a 100644 --- a/firmware/target/mips/ingenic_x1000/boot-x1000.c +++ b/firmware/target/mips/ingenic_x1000/boot-x1000.c | |||
@@ -267,7 +267,7 @@ void x1000_dualboot_init_uart2(void) | |||
267 | 267 | ||
268 | int x1000_dualboot_load_pdma_fw(void) | 268 | int x1000_dualboot_load_pdma_fw(void) |
269 | { | 269 | { |
270 | nand_drv* n = nand_init(); | 270 | struct nand_drv* n = nand_init(); |
271 | nand_lock(n); | 271 | nand_lock(n); |
272 | 272 | ||
273 | int ret = nand_open(n); | 273 | int ret = nand_open(n); |
diff --git a/firmware/target/mips/ingenic_x1000/installer-x1000.c b/firmware/target/mips/ingenic_x1000/installer-x1000.c index 66aa42d4a1..48850f8a62 100644 --- a/firmware/target/mips/ingenic_x1000/installer-x1000.c +++ b/firmware/target/mips/ingenic_x1000/installer-x1000.c | |||
@@ -65,7 +65,7 @@ static const int num_updates = sizeof(updates) / sizeof(struct update_part); | |||
65 | /* calculate the offset and length of the update image; this is constant | 65 | /* calculate the offset and length of the update image; this is constant |
66 | * for a given target, based on the update parts and the NAND chip geometry. | 66 | * for a given target, based on the update parts and the NAND chip geometry. |
67 | */ | 67 | */ |
68 | static void get_image_loc(nand_drv* ndrv, size_t* offptr, size_t* lenptr) | 68 | static void get_image_loc(struct nand_drv* ndrv, size_t* offptr, size_t* lenptr) |
69 | { | 69 | { |
70 | size_t blk_size = ndrv->chip->page_size << ndrv->chip->log2_ppb; | 70 | size_t blk_size = ndrv->chip->page_size << ndrv->chip->log2_ppb; |
71 | size_t img_off = 0; | 71 | size_t img_off = 0; |
@@ -119,7 +119,7 @@ struct updater { | |||
119 | size_t img_len; /* image length in flash = size of the buffer */ | 119 | size_t img_len; /* image length in flash = size of the buffer */ |
120 | 120 | ||
121 | mtar_t* tar; | 121 | mtar_t* tar; |
122 | nand_drv* ndrv; | 122 | struct nand_drv* ndrv; |
123 | }; | 123 | }; |
124 | 124 | ||
125 | static int updater_init(struct updater* u) | 125 | static int updater_init(struct updater* u) |
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index 382fd761b3..c740623d86 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
@@ -24,7 +24,7 @@ | |||
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include <string.h> | 25 | #include <string.h> |
26 | 26 | ||
27 | const nand_chip supported_nand_chips[] = { | 27 | const struct nand_chip supported_nand_chips[] = { |
28 | #if defined(FIIO_M3K) || defined(SHANLING_Q1) || defined(EROS_QN) | 28 | #if defined(FIIO_M3K) || defined(SHANLING_Q1) || defined(EROS_QN) |
29 | { | 29 | { |
30 | /* ATO25D1GA */ | 30 | /* ATO25D1GA */ |
@@ -51,14 +51,13 @@ const nand_chip supported_nand_chips[] = { | |||
51 | #endif | 51 | #endif |
52 | }; | 52 | }; |
53 | 53 | ||
54 | const size_t nr_supported_nand_chips = | 54 | const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips); |
55 | sizeof(supported_nand_chips) / sizeof(nand_chip); | ||
56 | 55 | ||
57 | static nand_drv static_nand_drv; | 56 | static struct nand_drv static_nand_drv; |
58 | static uint8_t static_scratch_buf[NAND_DRV_SCRATCHSIZE] CACHEALIGN_ATTR; | 57 | static uint8_t static_scratch_buf[NAND_DRV_SCRATCHSIZE] CACHEALIGN_ATTR; |
59 | static uint8_t static_page_buf[NAND_DRV_MAXPAGESIZE] CACHEALIGN_ATTR; | 58 | static uint8_t static_page_buf[NAND_DRV_MAXPAGESIZE] CACHEALIGN_ATTR; |
60 | 59 | ||
61 | nand_drv* nand_init(void) | 60 | struct nand_drv* nand_init(void) |
62 | { | 61 | { |
63 | static bool inited = false; | 62 | static bool inited = false; |
64 | if(!inited) { | 63 | if(!inited) { |
@@ -71,19 +70,19 @@ nand_drv* nand_init(void) | |||
71 | return &static_nand_drv; | 70 | return &static_nand_drv; |
72 | } | 71 | } |
73 | 72 | ||
74 | static uint8_t nand_get_reg(nand_drv* drv, uint8_t reg) | 73 | static uint8_t nand_get_reg(struct nand_drv* drv, uint8_t reg) |
75 | { | 74 | { |
76 | sfc_exec(NANDCMD_GET_FEATURE, reg, drv->scratch_buf, 1|SFC_READ); | 75 | sfc_exec(NANDCMD_GET_FEATURE, reg, drv->scratch_buf, 1|SFC_READ); |
77 | return drv->scratch_buf[0]; | 76 | return drv->scratch_buf[0]; |
78 | } | 77 | } |
79 | 78 | ||
80 | static void nand_set_reg(nand_drv* drv, uint8_t reg, uint8_t val) | 79 | static void nand_set_reg(struct nand_drv* drv, uint8_t reg, uint8_t val) |
81 | { | 80 | { |
82 | drv->scratch_buf[0] = val; | 81 | drv->scratch_buf[0] = val; |
83 | sfc_exec(NANDCMD_SET_FEATURE, reg, drv->scratch_buf, 1|SFC_WRITE); | 82 | sfc_exec(NANDCMD_SET_FEATURE, reg, drv->scratch_buf, 1|SFC_WRITE); |
84 | } | 83 | } |
85 | 84 | ||
86 | static void nand_upd_reg(nand_drv* drv, uint8_t reg, uint8_t msk, uint8_t val) | 85 | static void nand_upd_reg(struct nand_drv* drv, uint8_t reg, uint8_t msk, uint8_t val) |
87 | { | 86 | { |
88 | uint8_t x = nand_get_reg(drv, reg); | 87 | uint8_t x = nand_get_reg(drv, reg); |
89 | x &= ~msk; | 88 | x &= ~msk; |
@@ -91,7 +90,7 @@ static void nand_upd_reg(nand_drv* drv, uint8_t reg, uint8_t msk, uint8_t val) | |||
91 | nand_set_reg(drv, reg, x); | 90 | nand_set_reg(drv, reg, x); |
92 | } | 91 | } |
93 | 92 | ||
94 | static bool identify_chip(nand_drv* drv) | 93 | static bool identify_chip(struct nand_drv* drv) |
95 | { | 94 | { |
96 | /* Read ID command has some variations; Linux handles these 3: | 95 | /* Read ID command has some variations; Linux handles these 3: |
97 | * - no address or dummy bytes | 96 | * - no address or dummy bytes |
@@ -106,7 +105,7 @@ static bool identify_chip(nand_drv* drv) | |||
106 | drv->dev_id2 = drv->scratch_buf[2]; | 105 | drv->dev_id2 = drv->scratch_buf[2]; |
107 | 106 | ||
108 | for(size_t i = 0; i < nr_supported_nand_chips; ++i) { | 107 | for(size_t i = 0; i < nr_supported_nand_chips; ++i) { |
109 | const nand_chip* chip = &supported_nand_chips[i]; | 108 | const struct nand_chip* chip = &supported_nand_chips[i]; |
110 | if(chip->mf_id != drv->mf_id || chip->dev_id != drv->dev_id) | 109 | if(chip->mf_id != drv->mf_id || chip->dev_id != drv->dev_id) |
111 | continue; | 110 | continue; |
112 | 111 | ||
@@ -121,13 +120,13 @@ static bool identify_chip(nand_drv* drv) | |||
121 | return false; | 120 | return false; |
122 | } | 121 | } |
123 | 122 | ||
124 | static void setup_chip_data(nand_drv* drv) | 123 | static void setup_chip_data(struct nand_drv* drv) |
125 | { | 124 | { |
126 | drv->ppb = 1 << drv->chip->log2_ppb; | 125 | drv->ppb = 1 << drv->chip->log2_ppb; |
127 | drv->fpage_size = drv->chip->page_size + drv->chip->oob_size; | 126 | drv->fpage_size = drv->chip->page_size + drv->chip->oob_size; |
128 | } | 127 | } |
129 | 128 | ||
130 | static void setup_chip_commands(nand_drv* drv) | 129 | static void setup_chip_commands(struct nand_drv* drv) |
131 | { | 130 | { |
132 | /* Select commands appropriate for the chip */ | 131 | /* Select commands appropriate for the chip */ |
133 | drv->cmd_page_read = NANDCMD_PAGE_READ(drv->chip->row_cycles); | 132 | drv->cmd_page_read = NANDCMD_PAGE_READ(drv->chip->row_cycles); |
@@ -143,7 +142,7 @@ static void setup_chip_commands(nand_drv* drv) | |||
143 | } | 142 | } |
144 | } | 143 | } |
145 | 144 | ||
146 | static void setup_chip_registers(nand_drv* drv) | 145 | static void setup_chip_registers(struct nand_drv* drv) |
147 | { | 146 | { |
148 | /* Set chip registers to enter normal operation */ | 147 | /* Set chip registers to enter normal operation */ |
149 | if(drv->chip->flags & NAND_CHIPFLAG_HAS_QE_BIT) { | 148 | if(drv->chip->flags & NAND_CHIPFLAG_HAS_QE_BIT) { |
@@ -159,7 +158,7 @@ static void setup_chip_registers(nand_drv* drv) | |||
159 | nand_set_reg(drv, FREG_PROT, FREG_PROT_UNLOCK); | 158 | nand_set_reg(drv, FREG_PROT, FREG_PROT_UNLOCK); |
160 | } | 159 | } |
161 | 160 | ||
162 | int nand_open(nand_drv* drv) | 161 | int nand_open(struct nand_drv* drv) |
163 | { | 162 | { |
164 | if(drv->refcount > 0) { | 163 | if(drv->refcount > 0) { |
165 | drv->refcount++; | 164 | drv->refcount++; |
@@ -193,7 +192,7 @@ int nand_open(nand_drv* drv) | |||
193 | return NAND_SUCCESS; | 192 | return NAND_SUCCESS; |
194 | } | 193 | } |
195 | 194 | ||
196 | void nand_close(nand_drv* drv) | 195 | void nand_close(struct nand_drv* drv) |
197 | { | 196 | { |
198 | --drv->refcount; | 197 | --drv->refcount; |
199 | if(drv->refcount > 0) | 198 | if(drv->refcount > 0) |
@@ -207,7 +206,7 @@ void nand_close(nand_drv* drv) | |||
207 | sfc_close(); | 206 | sfc_close(); |
208 | } | 207 | } |
209 | 208 | ||
210 | static uint8_t nand_wait_busy(nand_drv* drv) | 209 | static uint8_t nand_wait_busy(struct nand_drv* drv) |
211 | { | 210 | { |
212 | uint8_t reg; | 211 | uint8_t reg; |
213 | do { | 212 | do { |
@@ -216,7 +215,7 @@ static uint8_t nand_wait_busy(nand_drv* drv) | |||
216 | return reg; | 215 | return reg; |
217 | } | 216 | } |
218 | 217 | ||
219 | int nand_block_erase(nand_drv* drv, nand_block_t block) | 218 | int nand_block_erase(struct nand_drv* drv, nand_block_t block) |
220 | { | 219 | { |
221 | sfc_exec(NANDCMD_WR_EN, 0, NULL, 0); | 220 | sfc_exec(NANDCMD_WR_EN, 0, NULL, 0); |
222 | sfc_exec(drv->cmd_block_erase, block, NULL, 0); | 221 | sfc_exec(drv->cmd_block_erase, block, NULL, 0); |
@@ -228,7 +227,7 @@ int nand_block_erase(nand_drv* drv, nand_block_t block) | |||
228 | return NAND_SUCCESS; | 227 | return NAND_SUCCESS; |
229 | } | 228 | } |
230 | 229 | ||
231 | int nand_page_program(nand_drv* drv, nand_page_t page, const void* buffer) | 230 | int nand_page_program(struct nand_drv* drv, nand_page_t page, const void* buffer) |
232 | { | 231 | { |
233 | sfc_exec(NANDCMD_WR_EN, 0, NULL, 0); | 232 | sfc_exec(NANDCMD_WR_EN, 0, NULL, 0); |
234 | sfc_exec(drv->cmd_program_load, 0, (void*)buffer, drv->fpage_size|SFC_WRITE); | 233 | sfc_exec(drv->cmd_program_load, 0, (void*)buffer, drv->fpage_size|SFC_WRITE); |
@@ -241,7 +240,7 @@ int nand_page_program(nand_drv* drv, nand_page_t page, const void* buffer) | |||
241 | return NAND_SUCCESS; | 240 | return NAND_SUCCESS; |
242 | } | 241 | } |
243 | 242 | ||
244 | int nand_page_read(nand_drv* drv, nand_page_t page, void* buffer) | 243 | int nand_page_read(struct nand_drv* drv, nand_page_t page, void* buffer) |
245 | { | 244 | { |
246 | sfc_exec(drv->cmd_page_read, page, NULL, 0); | 245 | sfc_exec(drv->cmd_page_read, page, NULL, 0); |
247 | nand_wait_busy(drv); | 246 | nand_wait_busy(drv); |
@@ -249,7 +248,7 @@ int nand_page_read(nand_drv* drv, nand_page_t page, void* buffer) | |||
249 | return NAND_SUCCESS; | 248 | return NAND_SUCCESS; |
250 | } | 249 | } |
251 | 250 | ||
252 | int nand_read_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer) | 251 | int nand_read_bytes(struct nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer) |
253 | { | 252 | { |
254 | if(byte_len == 0) | 253 | if(byte_len == 0) |
255 | return NAND_SUCCESS; | 254 | return NAND_SUCCESS; |
@@ -277,7 +276,7 @@ int nand_read_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* | |||
277 | return NAND_SUCCESS; | 276 | return NAND_SUCCESS; |
278 | } | 277 | } |
279 | 278 | ||
280 | int nand_write_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer) | 279 | int nand_write_bytes(struct nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer) |
281 | { | 280 | { |
282 | if(byte_len == 0) | 281 | if(byte_len == 0) |
283 | return NAND_SUCCESS; | 282 | return NAND_SUCCESS; |
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.h b/firmware/target/mips/ingenic_x1000/nand-x1000.h index 176897e4f2..dda54eb5c6 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.h +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.h | |||
@@ -95,7 +95,7 @@ | |||
95 | typedef uint32_t nand_block_t; | 95 | typedef uint32_t nand_block_t; |
96 | typedef uint32_t nand_page_t; | 96 | typedef uint32_t nand_page_t; |
97 | 97 | ||
98 | typedef struct nand_chip { | 98 | struct nand_chip { |
99 | /* Manufacturer and device ID bytes */ | 99 | /* Manufacturer and device ID bytes */ |
100 | uint8_t mf_id; | 100 | uint8_t mf_id; |
101 | uint8_t dev_id; | 101 | uint8_t dev_id; |
@@ -126,9 +126,9 @@ typedef struct nand_chip { | |||
126 | 126 | ||
127 | /* Chip specific flags */ | 127 | /* Chip specific flags */ |
128 | uint32_t flags; | 128 | uint32_t flags; |
129 | } nand_chip; | 129 | }; |
130 | 130 | ||
131 | typedef struct nand_drv { | 131 | struct nand_drv { |
132 | /* NAND access lock. Needs to be held during any operations. */ | 132 | /* NAND access lock. Needs to be held during any operations. */ |
133 | struct mutex mutex; | 133 | struct mutex mutex; |
134 | 134 | ||
@@ -150,7 +150,7 @@ typedef struct nand_drv { | |||
150 | uint8_t* page_buf; | 150 | uint8_t* page_buf; |
151 | 151 | ||
152 | /* Pointer to the chip data. */ | 152 | /* Pointer to the chip data. */ |
153 | const nand_chip* chip; | 153 | const struct nand_chip* chip; |
154 | 154 | ||
155 | /* Pages per block = 1 << chip->log2_ppb */ | 155 | /* Pages per block = 1 << chip->log2_ppb */ |
156 | unsigned ppb; | 156 | unsigned ppb; |
@@ -169,9 +169,9 @@ typedef struct nand_drv { | |||
169 | uint32_t cmd_program_load; | 169 | uint32_t cmd_program_load; |
170 | uint32_t cmd_program_execute; | 170 | uint32_t cmd_program_execute; |
171 | uint32_t cmd_block_erase; | 171 | uint32_t cmd_block_erase; |
172 | } nand_drv; | 172 | }; |
173 | 173 | ||
174 | extern const nand_chip supported_nand_chips[]; | 174 | extern const struct nand_chip supported_nand_chips[]; |
175 | extern const size_t nr_supported_nand_chips; | 175 | extern const size_t nr_supported_nand_chips; |
176 | 176 | ||
177 | /* Return the static NAND driver instance. | 177 | /* Return the static NAND driver instance. |
@@ -179,14 +179,14 @@ extern const size_t nr_supported_nand_chips; | |||
179 | * ALL normal Rockbox code should use this instance. The SPL does not | 179 | * ALL normal Rockbox code should use this instance. The SPL does not |
180 | * use it, because it needs to manually place buffers in external RAM. | 180 | * use it, because it needs to manually place buffers in external RAM. |
181 | */ | 181 | */ |
182 | extern nand_drv* nand_init(void); | 182 | extern struct nand_drv* nand_init(void); |
183 | 183 | ||
184 | static inline void nand_lock(nand_drv* drv) | 184 | static inline void nand_lock(struct nand_drv* drv) |
185 | { | 185 | { |
186 | mutex_lock(&drv->mutex); | 186 | mutex_lock(&drv->mutex); |
187 | } | 187 | } |
188 | 188 | ||
189 | static inline void nand_unlock(nand_drv* drv) | 189 | static inline void nand_unlock(struct nand_drv* drv) |
190 | { | 190 | { |
191 | mutex_unlock(&drv->mutex); | 191 | mutex_unlock(&drv->mutex); |
192 | } | 192 | } |
@@ -200,8 +200,8 @@ static inline void nand_unlock(nand_drv* drv) | |||
200 | * | 200 | * |
201 | * These functions require the lock to be held. | 201 | * These functions require the lock to be held. |
202 | */ | 202 | */ |
203 | extern int nand_open(nand_drv* drv); | 203 | extern int nand_open(struct nand_drv* drv); |
204 | extern void nand_close(nand_drv* drv); | 204 | extern void nand_close(struct nand_drv* drv); |
205 | 205 | ||
206 | /* Read / program / erase operations. Buffer needs to be cache-aligned for DMA. | 206 | /* Read / program / erase operations. Buffer needs to be cache-aligned for DMA. |
207 | * Read and program operate on full page data, ie. including OOB data areas. | 207 | * Read and program operate on full page data, ie. including OOB data areas. |
@@ -209,15 +209,15 @@ extern void nand_close(nand_drv* drv); | |||
209 | * NOTE: ECC is not implemented. If it ever needs to be, these functions will | 209 | * NOTE: ECC is not implemented. If it ever needs to be, these functions will |
210 | * probably use ECC transparently. All code should be written to expect this. | 210 | * probably use ECC transparently. All code should be written to expect this. |
211 | */ | 211 | */ |
212 | extern int nand_block_erase(nand_drv* drv, nand_block_t block); | 212 | extern int nand_block_erase(struct nand_drv* drv, nand_block_t block); |
213 | extern int nand_page_program(nand_drv* drv, nand_page_t page, const void* buffer); | 213 | extern int nand_page_program(struct nand_drv* drv, nand_page_t page, const void* buffer); |
214 | extern int nand_page_read(nand_drv* drv, nand_page_t page, void* buffer); | 214 | extern int nand_page_read(struct nand_drv* drv, nand_page_t page, void* buffer); |
215 | 215 | ||
216 | /* Wrappers to read/write bytes. For simple access to the main data area only. | 216 | /* Wrappers to read/write bytes. For simple access to the main data area only. |
217 | * The write address / length must align to a block boundary. Reads do not have | 217 | * The write address / length must align to a block boundary. Reads do not have |
218 | * any alignment requirement. OOB data is never read, and is written as 0xff. | 218 | * any alignment requirement. OOB data is never read, and is written as 0xff. |
219 | */ | 219 | */ |
220 | extern int nand_read_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer); | 220 | extern int nand_read_bytes(struct nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer); |
221 | extern int nand_write_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer); | 221 | extern int nand_write_bytes(struct nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer); |
222 | 222 | ||
223 | #endif /* __NAND_X1000_H__ */ | 223 | #endif /* __NAND_X1000_H__ */ |
diff --git a/firmware/target/mips/ingenic_x1000/spl-nand-x1000.c b/firmware/target/mips/ingenic_x1000/spl-nand-x1000.c index 82a05abf75..24eb42081e 100644 --- a/firmware/target/mips/ingenic_x1000/spl-nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/spl-nand-x1000.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include "gpio-x1000.h" | 23 | #include "gpio-x1000.h" |
24 | #include "nand-x1000.h" | 24 | #include "nand-x1000.h" |
25 | 25 | ||
26 | static nand_drv* ndrv = NULL; | 26 | static struct nand_drv* ndrv = NULL; |
27 | 27 | ||
28 | int spl_storage_open(void) | 28 | int spl_storage_open(void) |
29 | { | 29 | { |
@@ -31,7 +31,7 @@ int spl_storage_open(void) | |||
31 | gpioz_configure(GPIO_A, 0x3f << 26, GPIOF_DEVICE(1)); | 31 | gpioz_configure(GPIO_A, 0x3f << 26, GPIOF_DEVICE(1)); |
32 | 32 | ||
33 | /* Allocate NAND driver manually in DRAM */ | 33 | /* Allocate NAND driver manually in DRAM */ |
34 | ndrv = spl_alloc(sizeof(nand_drv)); | 34 | ndrv = spl_alloc(sizeof(struct nand_drv)); |
35 | ndrv->page_buf = spl_alloc(NAND_DRV_MAXPAGESIZE); | 35 | ndrv->page_buf = spl_alloc(NAND_DRV_MAXPAGESIZE); |
36 | ndrv->scratch_buf = spl_alloc(NAND_DRV_SCRATCHSIZE); | 36 | ndrv->scratch_buf = spl_alloc(NAND_DRV_SCRATCHSIZE); |
37 | ndrv->refcount = 0; | 37 | ndrv->refcount = 0; |