2 files changed, 11 insertions, 0 deletions

diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index 47f73b9f4c..b559aa3665 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -147,6 +147,8 @@
 
 /* clock control */
 #define CLOCK_SOURCE    (*(volatile unsigned long *)(0x60006020))
+#define MLCD_SCLK_DIV   (*(volatile unsigned long *)(0x6000602c))
+        /* bits 0..1: Mono LCD bridge serial clock divider: 1 / (n+1) */
 #define PLL_CONTROL     (*(volatile unsigned long *)(0x60006034))
 #define PLL_STATUS      (*(volatile unsigned long *)(0x6000603c))
 #define ADC_CLOCK_SRC   (*(volatile unsigned long *)(0x60006094))
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index 0f24997451..a1c4d1639e 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -178,6 +178,9 @@ static void pp_set_cpu_frequency(long frequency)
       case CPUFREQ_MAX:
         CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
         DEV_TIMING1  = 0x00000303;
+#ifdef IPOD_MINI2G
+        MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
+#endif
 #if CONFIG_CPU == PP5020
         PLL_CONTROL  = 0x8a020a03;  /* 10/3 * 24MHz */
         PLL_STATUS   = 0xd19b;      /* unlock frequencies > 66MHz */
@@ -196,6 +199,9 @@ static void pp_set_cpu_frequency(long frequency)
       case CPUFREQ_NORMAL:
         CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
         DEV_TIMING1  = 0x00000303;
+#ifdef IPOD_MINI2G
+        MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
+#endif
 #if CONFIG_CPU == PP5020
         PLL_CONTROL  = 0x8a020504;  /* 5/4 * 24MHz */
         scale_suspend_core(false);
@@ -220,6 +226,9 @@ static void pp_set_cpu_frequency(long frequency)
       default:
         CLOCK_SOURCE = 0x10002222;  /* source #1, #2, #3, #4: 24MHz */
         DEV_TIMING1  = 0x00000303;
+#ifdef IPOD_MINI2G
+        MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
+#endif
         PLL_CONTROL &= ~0x80000000; /* disable PLL */
         cpu_frequency = CPUFREQ_DEFAULT;
         PROC_CTL(CURRENT_CORE) = 0x4800001f; nop;