diff options
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/system-target.h | 9 | ||||
-rw-r--r-- | firmware/target/arm/mmu-arm.c | 16 |
2 files changed, 18 insertions, 7 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index 17f1593f62..e48b5d1ed1 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h | |||
@@ -42,8 +42,13 @@ static inline void invalidate_icache(void) | |||
42 | asm volatile( | 42 | asm volatile( |
43 | /* Clean and invalidate entire data cache */ | 43 | /* Clean and invalidate entire data cache */ |
44 | "mcr p15, 0, %0, c7, c14, 0 \n" | 44 | "mcr p15, 0, %0, c7, c14, 0 \n" |
45 | /* Invalidate entire instruction cache */ | 45 | /* Invalidate entire intruction cache |
46 | * Also flushes the branch target cache */ | ||
46 | "mcr p15, 0, %0, c7, c5, 0 \n" | 47 | "mcr p15, 0, %0, c7, c5, 0 \n" |
48 | /* Data synchronization barrier */ | ||
49 | "mcr p15, 0, %0, c7, c10, 4 \n" | ||
50 | /* Flush prefetch buffer */ | ||
51 | "mcr p15, 0, %0, c7, c5, 4 \n" | ||
47 | : : "r"(0) | 52 | : : "r"(0) |
48 | ); | 53 | ); |
49 | } | 54 | } |
@@ -54,6 +59,8 @@ static inline void flush_icache(void) | |||
54 | asm volatile ( | 59 | asm volatile ( |
55 | /* Clean entire data cache */ | 60 | /* Clean entire data cache */ |
56 | "mcr p15, 0, %0, c7, c10, 0 \n" | 61 | "mcr p15, 0, %0, c7, c10, 0 \n" |
62 | /* Data synchronization barrier */ | ||
63 | "mcr p15, 0, r2, c7, c10, 4 \n" | ||
57 | : : "r"(0) | 64 | : : "r"(0) |
58 | ); | 65 | ); |
59 | } | 66 | } |
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c index 5fa05d1dc6..ffca7a43ee 100644 --- a/firmware/target/arm/mmu-arm.c +++ b/firmware/target/arm/mmu-arm.c | |||
@@ -90,9 +90,11 @@ void enable_mmu(void) { | |||
90 | void __attribute__((naked)) invalidate_dcache_range(const void *base, unsigned int size) | 90 | void __attribute__((naked)) invalidate_dcache_range(const void *base, unsigned int size) |
91 | { | 91 | { |
92 | asm volatile( | 92 | asm volatile( |
93 | "add r1, r1, r0 \n" | 93 | "add r1, r1, r0 \n" |
94 | "mcrr p15, 0, r1, r0, c14 \n" | 94 | "mov r2, #0 \n" |
95 | "bx lr \n" | 95 | "mcrr p15, 0, r1, r0, c14 \n" /* Clean and invalidate dcache range */ |
96 | "mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */ | ||
97 | "bx lr \n" | ||
96 | ); | 98 | ); |
97 | (void)base; (void)size; | 99 | (void)base; (void)size; |
98 | } | 100 | } |
@@ -140,9 +142,11 @@ void invalidate_dcache_range(const void *base, unsigned int size) { | |||
140 | void __attribute__((naked)) clean_dcache_range(const void *base, unsigned int size) | 142 | void __attribute__((naked)) clean_dcache_range(const void *base, unsigned int size) |
141 | { | 143 | { |
142 | asm volatile( | 144 | asm volatile( |
143 | "add r1, r1, r0 \n" | 145 | "add r1, r1, r0 \n" |
144 | "mcrr p15, 0, r1, r0, c12 \n" | 146 | "mov r2, #0 \n" |
145 | "bx lr \n" | 147 | "mcrr p15, 0, r1, r0, c12 \n" /* Clean dcache range */ |
148 | "mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */ | ||
149 | "bx lr \n" | ||
146 | ); | 150 | ); |
147 | (void)base; (void)size; | 151 | (void)base; (void)size; |
148 | } | 152 | } |