diff options
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 31 |
1 files changed, 19 insertions, 12 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 923f4e7c43..560e067510 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -40,9 +40,13 @@ | |||
40 | * | 40 | * |
41 | * The CLOCK_DIV macro does a pretty good job at selecting divider values but | 41 | * The CLOCK_DIV macro does a pretty good job at selecting divider values but |
42 | * you can always override it by choosing your own value and commenting out the | 42 | * you can always override it by choosing your own value and commenting out the |
43 | * macro. If you are going to use AS3525_FCLK_PREDIV or AS3525_PCLK_DIV1 you | 43 | * macro. AS3525_FCLK_PREDIV values other than 0 allow you to choose frequencies |
44 | * will have to do a manual calculation. I have included USB & PLLB for future | 44 | * from lines below the main PLL frequency lines. AS3525_FCLK_POSTDIV |
45 | * use but commented them out for now. | 45 | * will be calculated automagically depending on the value you have selected |
46 | * for AS3525_FCLK_FREQ. You may add more PLL frequencies by simply commenting | ||
47 | * out the current #defines for AS3525_PLLA_FREQ & AS3525_PLLA_SETTING and | ||
48 | * adding a #define for FREQ and divider setting to produce that frequency.I | ||
49 | * have included USB & PLLB for future use but commented them out for now. | ||
46 | */ | 50 | */ |
47 | 51 | ||
48 | /* Clock Sources */ | 52 | /* Clock Sources */ |
@@ -51,8 +55,8 @@ | |||
51 | //#define AS3525_CLK_PLLB 2 | 55 | //#define AS3525_CLK_PLLB 2 |
52 | #define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ | 56 | #define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ |
53 | 57 | ||
58 | /** ************ Change these to reconfigure clocking scheme *******************/ | ||
54 | /* PLL frequencies and settings*/ | 59 | /* PLL frequencies and settings*/ |
55 | |||
56 | #define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */ | 60 | #define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */ |
57 | /* FCLK_PREDIV-> *7/8 = 217MHz 108.5 ,72.3, 54.25, 43.4, 36.17 */ | 61 | /* FCLK_PREDIV-> *7/8 = 217MHz 108.5 ,72.3, 54.25, 43.4, 36.17 */ |
58 | /* *6/8 = 186MHz 93, 62, 46.5, 37.2 */ | 62 | /* *6/8 = 186MHz 93, 62, 46.5, 37.2 */ |
@@ -69,11 +73,14 @@ | |||
69 | //#define AS3525_PLLB_FREQ | 73 | //#define AS3525_PLLB_FREQ |
70 | //#define AS3525_PLLB_SETTING | 74 | //#define AS3525_PLLB_SETTING |
71 | 75 | ||
72 | /** ************ Change these to reconfigure clocking scheme *******************/ | 76 | #define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ |
77 | /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */ | ||
73 | 78 | ||
74 | #define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ | 79 | #define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ |
75 | #define AS3525_PCLK_FREQ 62000000 /* Initial PCLK frequency */ | 80 | #define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ |
76 | #define AS3525_DBOP_FREQ AS3525_PCLK_FREQ /* Initial DBOP frequency */ | 81 | /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ |
82 | #define AS3525_PCLK_FREQ AS3525_DRAM_FREQ/1 /* PCLK divided from DRAM freq */ | ||
83 | #define AS3525_DBOP_FREQ AS3525_PCLK_FREQ/1 /* DBOP divided from PCLK freq */ | ||
77 | 84 | ||
78 | /** ****************************************************************************/ | 85 | /** ****************************************************************************/ |
79 | 86 | ||
@@ -89,18 +96,18 @@ | |||
89 | 96 | ||
90 | /* FCLK */ | 97 | /* FCLK */ |
91 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA | 98 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA |
92 | #define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ | ||
93 | #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ | 99 | #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ |
94 | 100 | ||
95 | /* PCLK */ | 101 | /* PCLK */ |
96 | #ifdef ASYNCHRONOUS_BUS | 102 | #ifdef ASYNCHRONOUS_BUS |
97 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ | 103 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ |
98 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1)/*div=1/(n+1)*/ | 104 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/ |
99 | #else | 105 | #else |
100 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */ | 106 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */ |
101 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_PCLK_FREQ) - 1) /*div=1/(n+1)*/ | 107 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ |
102 | #endif | 108 | #endif |
103 | #define AS3525_PCLK_DIV1 0 /* div = 1/(n+1) unable to use successfuly so far*/ | 109 | /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ |
110 | #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ | ||
104 | 111 | ||
105 | /* PCLK as Source */ | 112 | /* PCLK as Source */ |
106 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ | 113 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ |