diff options
-rw-r--r-- | bootloader/ipod.c | 14 | ||||
-rw-r--r-- | firmware/export/pp5020.h | 113 | ||||
-rw-r--r-- | firmware/rolo.c | 8 | ||||
-rw-r--r-- | firmware/system.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/crt0-pp.S | 2 | ||||
-rw-r--r-- | firmware/target/arm/ipod/backlight-nano_video.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/ipod/lcd-color_nano.c | 10 | ||||
-rw-r--r-- | firmware/target/arm/ipod/lcd-gray.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/sandisk/sansa-e200/ata-e200.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/sandisk/sansa-e200/lcd-e200.c | 8 |
10 files changed, 100 insertions, 77 deletions
diff --git a/bootloader/ipod.c b/bootloader/ipod.c index 73b4fffc71..0600ea62c1 100644 --- a/bootloader/ipod.c +++ b/bootloader/ipod.c | |||
@@ -82,14 +82,14 @@ static void ser_opto_keypad_cfg(int val) | |||
82 | { | 82 | { |
83 | int start_time; | 83 | int start_time; |
84 | 84 | ||
85 | outl(inl(0x6000d004) & ~0x80, 0x6000d004); | 85 | GPIOB_ENABLE &=~ 0x80; |
86 | 86 | ||
87 | outl(inl(0x7000c104) | 0xc000000, 0x7000c104); | 87 | outl(inl(0x7000c104) | 0xc000000, 0x7000c104); |
88 | outl(val, 0x7000c120); | 88 | outl(val, 0x7000c120); |
89 | outl(inl(0x7000c100) | 0x80000000, 0x7000c100); | 89 | outl(inl(0x7000c100) | 0x80000000, 0x7000c100); |
90 | 90 | ||
91 | outl(inl(0x6000d024) & ~0x10, 0x6000d024); | 91 | GPIOB_OUTPUT_VAL &=~ 0x10; |
92 | outl(inl(0x6000d014) | 0x10, 0x6000d014); | 92 | GPIOB_OUTPUT_EN |= 0x10; |
93 | 93 | ||
94 | start_time = USEC_TIMER; | 94 | start_time = USEC_TIMER; |
95 | do { | 95 | do { |
@@ -100,9 +100,9 @@ static void ser_opto_keypad_cfg(int val) | |||
100 | 100 | ||
101 | outl(inl(0x7000c100) & ~0x80000000, 0x7000c100); | 101 | outl(inl(0x7000c100) & ~0x80000000, 0x7000c100); |
102 | 102 | ||
103 | outl(inl(0x6000d004) | 0x80, 0x6000d004); | 103 | GPIOB_ENABLE |= 0x80; |
104 | outl(inl(0x6000d024) | 0x10, 0x6000d024); | 104 | GPIOB_OUTPUT_VAL |= 0x10; |
105 | outl(inl(0x6000d014) & ~0x10, 0x6000d014); | 105 | GPIOB_OUTPUT_EN &=~0x10; |
106 | 106 | ||
107 | outl(inl(0x7000c104) | 0xc000000, 0x7000c104); | 107 | outl(inl(0x7000c104) | 0xc000000, 0x7000c104); |
108 | outl(inl(0x7000c100) | 0x60000000, 0x7000c100); | 108 | outl(inl(0x7000c100) | 0x60000000, 0x7000c100); |
@@ -253,7 +253,7 @@ void* main(void) | |||
253 | outl(((0x100 | 1) << 3), 0x6000d824); | 253 | outl(((0x100 | 1) << 3), 0x6000d824); |
254 | 254 | ||
255 | /* set port L07 on */ | 255 | /* set port L07 on */ |
256 | outl(((0x100 | 1) << 7), 0x6000d12c); | 256 | GPIOL_OUTPUT_VAL = ((0x100 | 1) << 7); |
257 | #elif CONFIG_BACKLIGHT==BL_IPOD3G | 257 | #elif CONFIG_BACKLIGHT==BL_IPOD3G |
258 | outl(inl(IPOD_LCD_BASE) | 0x2, IPOD_LCD_BASE); | 258 | outl(inl(IPOD_LCD_BASE) | 0x2, IPOD_LCD_BASE); |
259 | #endif | 259 | #endif |
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 60d14491e0..ade1f138a0 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h | |||
@@ -20,11 +20,72 @@ | |||
20 | #define __PP5020_H__ | 20 | #define __PP5020_H__ |
21 | 21 | ||
22 | /* All info gleaned and/or copied from the iPodLinux project. */ | 22 | /* All info gleaned and/or copied from the iPodLinux project. */ |
23 | |||
24 | /* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */ | ||
23 | #define DRAM_START 0x10000000 | 25 | #define DRAM_START 0x10000000 |
24 | 26 | ||
27 | /* Processor ID */ | ||
28 | #define PROCESSOR_ID (*(volatile unsigned long *)(0x60000000)) | ||
29 | |||
30 | #define PROC_ID_CPU 0x55 | ||
31 | #define PROC_ID_COP 0xaa | ||
32 | |||
33 | /* Interrupts */ | ||
34 | #define CPU_INT_EN (*(volatile unsigned long*)(0x60004024)) | ||
35 | #define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124)) | ||
36 | #define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028)) | ||
37 | #define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128)) | ||
38 | #define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000)) | ||
39 | #define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100)) | ||
40 | |||
41 | #define TIMER1_IRQ 0 | ||
42 | #define TIMER2_IRQ 1 | ||
43 | #define I2S_IRQ 10 | ||
44 | #define IDE_IRQ 23 | ||
45 | #define GPIO_IRQ (32+0) | ||
46 | #define SER0_IRQ (32+4) | ||
47 | #define SER1_IRQ (32+5) | ||
48 | #define I2C_IRQ (32+8) | ||
49 | |||
50 | #define TIMER1_MASK (1 << TIMER1_IRQ) | ||
51 | #define TIMER2_MASK (1 << TIMER2_IRQ) | ||
52 | #define I2S_MASK (1 << I2S_IRQ) | ||
53 | #define IDE_MASK (1 << IDE_IRQ) | ||
54 | #define GPIO_MASK (1 << (GPIO_IRQ-32)) | ||
55 | #define SER0_MASK (1 << (SER0_IRQ-32)) | ||
56 | #define SER1_MASK (1 << (SER1_IRQ-32)) | ||
57 | #define I2C_MASK (1 << (I2C_IRQ-32)) | ||
58 | |||
59 | /* Timers */ | ||
60 | #define TIMER1_CFG (*(volatile unsigned long *)(0x60005000)) | ||
61 | #define TIMER1_VAL (*(volatile unsigned long *)(0x60005004)) | ||
62 | #define TIMER2_CFG (*(volatile unsigned long *)(0x60005008)) | ||
63 | #define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c)) | ||
64 | #define USEC_TIMER (*(volatile unsigned long *)(0x60005010)) | ||
65 | |||
66 | /* Device Controller */ | ||
67 | #define DEV_RS (*(volatile unsigned long *)(0x60006004)) | ||
68 | #define DEV_EN (*(volatile unsigned long *)(0x6000600c)) | ||
69 | |||
70 | #define DEV_SYSTEM 0x4 | ||
71 | #define DEV_I2C 0x1000 | ||
72 | #define DEV_USB 0x400000 | ||
73 | |||
74 | /* Processors Control */ | ||
25 | #define CPU_CTL (*(volatile unsigned long *)(0x60007000)) | 75 | #define CPU_CTL (*(volatile unsigned long *)(0x60007000)) |
26 | #define COP_CTL (*(volatile unsigned long *)(0x60007004)) | 76 | #define COP_CTL (*(volatile unsigned long *)(0x60007004)) |
27 | 77 | ||
78 | #define PROC_SLEEP 0x80000000 | ||
79 | #define PROC_WAKE 0x0 | ||
80 | |||
81 | /* Cache Control */ | ||
82 | #define CACHE_CTL (*(volatile unsigned long *)(0x6000c000)) | ||
83 | |||
84 | #define CACHE_DISABLE 0 | ||
85 | #define CACHE_ENABLE 1 | ||
86 | #define CACHE_INIT 4 | ||
87 | |||
88 | /* GPIO Ports */ | ||
28 | #define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000)) | 89 | #define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000)) |
29 | #define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004)) | 90 | #define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004)) |
30 | #define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008)) | 91 | #define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008)) |
@@ -124,56 +185,24 @@ | |||
124 | #define GPIOK_INT_CLR (*(volatile unsigned long *)(0x6000d178)) | 185 | #define GPIOK_INT_CLR (*(volatile unsigned long *)(0x6000d178)) |
125 | #define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c)) | 186 | #define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c)) |
126 | 187 | ||
127 | #define DEV_RS (*(volatile unsigned long *)(0x60006004)) | 188 | /* Device initialization */ |
128 | #define DEV_EN (*(volatile unsigned long *)(0x6000600c)) | ||
129 | |||
130 | #define DEV_SYSTEM 0x4 | ||
131 | #define DEV_I2C 0x1000 | ||
132 | #define DEV_USB 0x400000 | ||
133 | |||
134 | #define DEV_INIT (*(volatile unsigned long *)(0x70000020)) | 189 | #define DEV_INIT (*(volatile unsigned long *)(0x70000020)) |
135 | 190 | ||
136 | #define INIT_USB 0x80000000 | 191 | #define INIT_USB 0x80000000 |
137 | 192 | ||
138 | #define TIMER1_CFG (*(volatile unsigned long *)(0x60005000)) | 193 | /* I2C */ |
139 | #define TIMER1_VAL (*(volatile unsigned long *)(0x60005004)) | ||
140 | #define TIMER2_CFG (*(volatile unsigned long *)(0x60005008)) | ||
141 | #define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c)) | ||
142 | #define USEC_TIMER (*(volatile unsigned long *)(0x60005010)) | ||
143 | |||
144 | #define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000)) | ||
145 | #define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100)) | ||
146 | #define CPU_INT_EN (*(volatile unsigned long*)(0x60004024)) | ||
147 | #define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124)) | ||
148 | #define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028)) | ||
149 | #define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128)) | ||
150 | |||
151 | #define TIMER1_IRQ 0 | ||
152 | #define TIMER2_IRQ 1 | ||
153 | #define I2S_IRQ 10 | ||
154 | #define IDE_IRQ 23 | ||
155 | #define GPIO_IRQ (32+0) | ||
156 | #define SER0_IRQ (32+4) | ||
157 | #define SER1_IRQ (32+5) | ||
158 | #define I2C_IRQ (32+8) | ||
159 | |||
160 | #define TIMER1_MASK (1 << TIMER1_IRQ) | ||
161 | #define TIMER2_MASK (1 << TIMER2_IRQ) | ||
162 | #define I2S_MASK (1 << I2S_IRQ) | ||
163 | #define IDE_MASK (1 << IDE_IRQ) | ||
164 | #define GPIO_MASK (1 << (GPIO_IRQ-32)) | ||
165 | #define SER0_MASK (1 << (SER0_IRQ-32)) | ||
166 | #define SER1_MASK (1 << (SER1_IRQ-32)) | ||
167 | #define I2C_MASK (1 << (I2C_IRQ-32)) | ||
168 | |||
169 | #define I2C_BASE 0x7000c000 | 194 | #define I2C_BASE 0x7000c000 |
170 | 195 | ||
196 | /* I2S */ | ||
171 | #define IISCONFIG (*(volatile unsigned long*)(0x70002800)) | 197 | #define IISCONFIG (*(volatile unsigned long*)(0x70002800)) |
172 | |||
173 | #define IISFIFO_CFG (*(volatile unsigned long*)(0x7000280c)) | 198 | #define IISFIFO_CFG (*(volatile unsigned long*)(0x7000280c)) |
174 | #define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) | 199 | #define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) |
175 | #define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) | 200 | #define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) |
176 | 201 | ||
202 | /* USB controller */ | ||
203 | #define USB_BASE 0xc5000000 | ||
204 | |||
205 | /* Memory controller */ | ||
177 | #define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000)) | 206 | #define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000)) |
178 | #define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004)) | 207 | #define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004)) |
179 | #define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008)) | 208 | #define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008)) |
@@ -183,10 +212,4 @@ | |||
183 | #define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018)) | 212 | #define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018)) |
184 | #define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c)) | 213 | #define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c)) |
185 | 214 | ||
186 | /* The PortalPlayer USB controller uses base address 0xc5000000 */ | ||
187 | #define USB_BASE 0xc5000000 | ||
188 | |||
189 | #define PROC_SLEEP 0x80000000 | ||
190 | #define PROC_WAKE 0x0 | ||
191 | |||
192 | #endif | 215 | #endif |
diff --git a/firmware/rolo.c b/firmware/rolo.c index 1489a8e695..4ac730b7ef 100644 --- a/firmware/rolo.c +++ b/firmware/rolo.c | |||
@@ -50,10 +50,10 @@ void rolo_restart_cop(void) | |||
50 | { | 50 | { |
51 | /* Invalidate cache */ | 51 | /* Invalidate cache */ |
52 | outl(inl(0xf000f044) | 0x6, 0xf000f044); | 52 | outl(inl(0xf000f044) | 0x6, 0xf000f044); |
53 | while ((inl(0x6000c000) & 0x8000) != 0) {} | 53 | while ((CACHE_CTL & 0x8000) != 0) {} |
54 | 54 | ||
55 | /* Disable cache */ | 55 | /* Disable cache */ |
56 | outl(0x0, 0x6000C000); | 56 | CACHE_CTL = CACHE_DISABLE; |
57 | 57 | ||
58 | /* Wait while RoLo loads the image into SDRAM */ | 58 | /* Wait while RoLo loads the image into SDRAM */ |
59 | /* TODO: Accept checksum failure gracefully */ | 59 | /* TODO: Accept checksum failure gracefully */ |
@@ -115,10 +115,10 @@ void rolo_restart(const unsigned char* source, unsigned char* dest, | |||
115 | 115 | ||
116 | /* Flush cache */ | 116 | /* Flush cache */ |
117 | outl(inl(0xf000f044) | 0x2, 0xf000f044); | 117 | outl(inl(0xf000f044) | 0x2, 0xf000f044); |
118 | while ((inl(0x6000c000) & 0x8000) != 0) {} | 118 | while ((CACHE_CTL & 0x8000) != 0) {} |
119 | 119 | ||
120 | /* Disable cache */ | 120 | /* Disable cache */ |
121 | outl(0x0, 0x6000C000); | 121 | CACHE_CTL = CACHE_DISABLE; |
122 | 122 | ||
123 | /* Reset the memory mapping registers to zero */ | 123 | /* Reset the memory mapping registers to zero */ |
124 | for (i=0;i<8;i++) | 124 | for (i=0;i<8;i++) |
diff --git a/firmware/system.c b/firmware/system.c index 463eec5053..a86d945093 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -648,7 +648,7 @@ void irq(void) | |||
648 | 648 | ||
649 | unsigned int current_core(void) | 649 | unsigned int current_core(void) |
650 | { | 650 | { |
651 | if(((*(volatile unsigned long *)(0x60000000)) & 0xff) == 0x55) | 651 | if((PROCESSOR_ID & 0xff) == PROC_ID_CPU) |
652 | { | 652 | { |
653 | return CPU; | 653 | return CPU; |
654 | } | 654 | } |
@@ -670,7 +670,7 @@ static void ipod_init_cache(void) | |||
670 | unsigned i; | 670 | unsigned i; |
671 | 671 | ||
672 | /* cache init mode? */ | 672 | /* cache init mode? */ |
673 | outl(0x4, 0x6000C000); | 673 | CACHE_CTL = CACHE_INIT; |
674 | 674 | ||
675 | /* PP5002 has 8KB cache */ | 675 | /* PP5002 has 8KB cache */ |
676 | for (i = 0xf0004000; i < 0xf0006000; i += 16) { | 676 | for (i = 0xf0004000; i < 0xf0006000; i += 16) { |
@@ -681,7 +681,7 @@ static void ipod_init_cache(void) | |||
681 | outl(0x3fc0, 0xf000f044); | 681 | outl(0x3fc0, 0xf000f044); |
682 | 682 | ||
683 | /* enable cache */ | 683 | /* enable cache */ |
684 | outl(0x1, 0x6000C000); | 684 | CACHE_CTL = CACHE_ENABLE; |
685 | 685 | ||
686 | for (i = 0x10000000; i < 0x10002000; i += 16) | 686 | for (i = 0x10000000; i < 0x10002000; i += 16) |
687 | inb(i); | 687 | inb(i); |
diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S index 892275e411..e0d1034f74 100644 --- a/firmware/target/arm/crt0-pp.S +++ b/firmware/target/arm/crt0-pp.S | |||
@@ -205,7 +205,7 @@ cop_init: | |||
205 | orr r1, r1, #0x6 | 205 | orr r1, r1, #0x6 |
206 | str r1, [r0] | 206 | str r1, [r0] |
207 | 207 | ||
208 | ldr r0, =0x6000c000 | 208 | ldr r0, =CACHE_CTRL |
209 | 1: | 209 | 1: |
210 | ldr r1, [r0] | 210 | ldr r1, [r0] |
211 | tst r1, #0x8000 | 211 | tst r1, #0x8000 |
diff --git a/firmware/target/arm/ipod/backlight-nano_video.c b/firmware/target/arm/ipod/backlight-nano_video.c index 5559709333..a5ef334d61 100644 --- a/firmware/target/arm/ipod/backlight-nano_video.c +++ b/firmware/target/arm/ipod/backlight-nano_video.c | |||
@@ -37,7 +37,7 @@ inline void __backlight_on(void) | |||
37 | outl(((0x100 | 1) << 3), 0x6000d824); | 37 | outl(((0x100 | 1) << 3), 0x6000d824); |
38 | 38 | ||
39 | /* set port L07 on */ | 39 | /* set port L07 on */ |
40 | outl(((0x100 | 1) << 7), 0x6000d12c); | 40 | GPIOL_OUTPUT_VAL = ((0x100 | 1) << 7); |
41 | } | 41 | } |
42 | 42 | ||
43 | inline void __backlight_off(void) | 43 | inline void __backlight_off(void) |
@@ -46,5 +46,5 @@ inline void __backlight_off(void) | |||
46 | outl(((0x100 | 0) << 3), 0x6000d824); | 46 | outl(((0x100 | 0) << 3), 0x6000d824); |
47 | 47 | ||
48 | /* set port L07 off */ | 48 | /* set port L07 off */ |
49 | outl(((0x100 | 0) << 7), 0x6000d12c); | 49 | GPIOL_OUTPUT_VAL = ((0x100 | 0) << 7); |
50 | } | 50 | } |
diff --git a/firmware/target/arm/ipod/lcd-color_nano.c b/firmware/target/arm/ipod/lcd-color_nano.c index 7da878ef14..6a29cbe680 100644 --- a/firmware/target/arm/ipod/lcd-color_nano.c +++ b/firmware/target/arm/ipod/lcd-color_nano.c | |||
@@ -115,9 +115,9 @@ void lcd_init_device(void) | |||
115 | int gpio_a01, gpio_a04; | 115 | int gpio_a01, gpio_a04; |
116 | 116 | ||
117 | /* A01 */ | 117 | /* A01 */ |
118 | gpio_a01 = (inl(0x6000D030) & 0x2) >> 1; | 118 | gpio_a01 = (GPIOA_INPUT_VAL & 0x2) >> 1; |
119 | /* A04 */ | 119 | /* A04 */ |
120 | gpio_a04 = (inl(0x6000D030) & 0x10) >> 4; | 120 | gpio_a04 = (GPIOA_INPUT_VAL & 0x10) >> 4; |
121 | 121 | ||
122 | if (((gpio_a01 << 1) | gpio_a04) == 0 || ((gpio_a01 << 1) | gpio_a04) == 2) { | 122 | if (((gpio_a01 << 1) | gpio_a04) == 0 || ((gpio_a01 << 1) | gpio_a04) == 2) { |
123 | lcd_type = 0; | 123 | lcd_type = 0; |
@@ -126,12 +126,12 @@ void lcd_init_device(void) | |||
126 | } | 126 | } |
127 | } | 127 | } |
128 | 128 | ||
129 | outl(inl(0x6000d004) | 0x4, 0x6000d004); /* B02 enable */ | 129 | GPIOB_ENABLE |= 0x4; /* B02 enable */ |
130 | outl(inl(0x6000d004) | 0x8, 0x6000d004); /* B03 enable */ | 130 | GPIOB_ENABLE |= 0x8; /* B03 enable */ |
131 | outl(inl(0x70000084) | 0x2000000, 0x70000084); /* D01 enable */ | 131 | outl(inl(0x70000084) | 0x2000000, 0x70000084); /* D01 enable */ |
132 | outl(inl(0x70000080) | 0x2000000, 0x70000080); /* D01 =1 */ | 132 | outl(inl(0x70000080) | 0x2000000, 0x70000080); /* D01 =1 */ |
133 | 133 | ||
134 | outl(inl(0x6000600c) | 0x20000, 0x6000600c); /* PWM enable */ | 134 | DEV_EN |= 0x20000; /* PWM enable */ |
135 | 135 | ||
136 | #elif CONFIG_LCD == LCD_IPODNANO | 136 | #elif CONFIG_LCD == LCD_IPODNANO |
137 | /* iPodLinux doesn't appear have any LCD init code for the Nano */ | 137 | /* iPodLinux doesn't appear have any LCD init code for the Nano */ |
diff --git a/firmware/target/arm/ipod/lcd-gray.c b/firmware/target/arm/ipod/lcd-gray.c index 620c4355c3..1493751c3b 100644 --- a/firmware/target/arm/ipod/lcd-gray.c +++ b/firmware/target/arm/ipod/lcd-gray.c | |||
@@ -133,12 +133,12 @@ void lcd_init_device(void) | |||
133 | lcd_cmd_and_data(R_ENTRY_MODE, 0x0000); | 133 | lcd_cmd_and_data(R_ENTRY_MODE, 0x0000); |
134 | 134 | ||
135 | #ifdef IPOD_4G | 135 | #ifdef IPOD_4G |
136 | outl(inl(0x6000d004) | 0x4, 0x6000d004); /* B02 enable */ | 136 | GPIOB_ENABLE |= 0x4; /* B02 enable */ |
137 | outl(inl(0x6000d004) | 0x8, 0x6000d004); /* B03 enable */ | 137 | GPIOB_ENABLE |= 0x8; /* B03 enable */ |
138 | outl(inl(0x70000084) | 0x2000000, 0x70000084); /* D01 enable */ | 138 | outl(inl(0x70000084) | 0x2000000, 0x70000084); /* D01 enable */ |
139 | outl(inl(0x70000080) | 0x2000000, 0x70000080); /* D01 =1 */ | 139 | outl(inl(0x70000080) | 0x2000000, 0x70000080); /* D01 =1 */ |
140 | 140 | ||
141 | outl(inl(0x6000600c) | 0x20000, 0x6000600c); /* PWM enable */ | 141 | DEV_EN |= 0x20000; /* PWM enable */ |
142 | #endif | 142 | #endif |
143 | } | 143 | } |
144 | 144 | ||
diff --git a/firmware/target/arm/sandisk/sansa-e200/ata-e200.c b/firmware/target/arm/sandisk/sansa-e200/ata-e200.c index 56f351c001..cf05397a78 100644 --- a/firmware/target/arm/sandisk/sansa-e200/ata-e200.c +++ b/firmware/target/arm/sandisk/sansa-e200/ata-e200.c | |||
@@ -364,9 +364,9 @@ void sd_init_device(void) | |||
364 | GPIOD_ENABLE |= (0x1f); | 364 | GPIOD_ENABLE |= (0x1f); |
365 | GPIOD_OUTPUT_EN |= (0x1f); | 365 | GPIOD_OUTPUT_EN |= (0x1f); |
366 | GPIOD_OUTPUT_VAL |= (0x1f); | 366 | GPIOD_OUTPUT_VAL |= (0x1f); |
367 | outl(inl(0x6000600c) | (1 << 14), 0x6000600c); | 367 | DEV_EN |= (1 << 14); /* Enable controller */ |
368 | outl(inl(0x60006004) | (1 << 14), 0x60006004); | 368 | DEV_RS |= (1 << 14); /* Reset controller */ |
369 | outl(inl(0x60006004) & ~(1 << 14), 0x60006004); /* Reset Controller? */ | 369 | DEV_RS &=~(1 << 14); /* Clear Reset */ |
370 | outl(0, 0x6000b000); | 370 | outl(0, 0x6000b000); |
371 | outl(0, 0x6000a000); /* Init DMA controller? */ | 371 | outl(0, 0x6000a000); /* Init DMA controller? */ |
372 | 372 | ||
diff --git a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c index 25bb6f04aa..e34ebd7c5a 100644 --- a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c +++ b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c | |||
@@ -110,7 +110,7 @@ static inline void cache_flush(void) | |||
110 | { | 110 | { |
111 | #ifndef BOOTLOADER | 111 | #ifndef BOOTLOADER |
112 | outl(inl(0xf000f044) | 0x2, 0xf000f044); | 112 | outl(inl(0xf000f044) | 0x2, 0xf000f044); |
113 | while ((inl(0x6000c000) & 0x8000) != 0) | 113 | while ((CACHE_CTL & 0x8000) != 0) |
114 | { | 114 | { |
115 | } | 115 | } |
116 | #endif | 116 | #endif |
@@ -141,12 +141,12 @@ inline void lcd_init_device(void) | |||
141 | outl(((inl(0x70000010) & (0x03ffffff)) | (0x15 << 26)), 0x70000010); | 141 | outl(((inl(0x70000010) & (0x03ffffff)) | (0x15 << 26)), 0x70000010); |
142 | outl(((inl(0x70000014) & (0x0fffffff)) | (0x5 << 28)), 0x70000014); | 142 | outl(((inl(0x70000014) & (0x0fffffff)) | (0x5 << 28)), 0x70000014); |
143 | outl((inl(0x70000020) & ~(0x3 << 10)), 0x70000020); | 143 | outl((inl(0x70000020) & ~(0x3 << 10)), 0x70000020); |
144 | outl((inl(0x6000600c) | (1 << 26)), 0x6000600c); /* Enable controller */ | 144 | DEV_EN |= (1 << 26); /* Enable controller */ |
145 | outl(0x6, 0x600060d0); | 145 | outl(0x6, 0x600060d0); |
146 | outl((inl(0x60006004) | (1 << 26)), 0x60006004); /* Reset controller? */ | 146 | DEV_RS |= (1 << 26); /* Reset controller */ |
147 | outl((inl(0x70000020) & ~(1 << 14)), 0x70000020); | 147 | outl((inl(0x70000020) & ~(1 << 14)), 0x70000020); |
148 | lcd_bus_idle(); | 148 | lcd_bus_idle(); |
149 | outl((inl(0x60006004) & ~(1 << 26)), 0x60006004); /* Clear reset? */ | 149 | DEV_RS &=~(1 << 26); /* Clear reset */ |
150 | udelay(1000); | 150 | udelay(1000); |
151 | 151 | ||
152 | LCD_REG_0 = (LCD_REG_0 & (0x00ffffff)) | (0x22 << 24); | 152 | LCD_REG_0 = (LCD_REG_0 & (0x00ffffff)) | (0x22 << 24); |