diff options
-rw-r--r-- | firmware/export/tcc780x.h | 3 | ||||
-rw-r--r-- | firmware/export/usb-tcc7xx.h | 16 |
2 files changed, 17 insertions, 2 deletions
diff --git a/firmware/export/tcc780x.h b/firmware/export/tcc780x.h index 22e046a445..ca6256bf06 100644 --- a/firmware/export/tcc780x.h +++ b/firmware/export/tcc780x.h | |||
@@ -224,4 +224,7 @@ | |||
224 | #define ECC_ERRDATA (*(volatile unsigned long *)0xF005B060) | 224 | #define ECC_ERRDATA (*(volatile unsigned long *)0xF005B060) |
225 | #define ECC_ERR (*(volatile unsigned long *)0xF005B070) | 225 | #define ECC_ERR (*(volatile unsigned long *)0xF005B070) |
226 | 226 | ||
227 | /* USB 2.0 device system MMR base address */ | ||
228 | #define USB_BASE 0xf0010000 | ||
229 | |||
227 | #endif | 230 | #endif |
diff --git a/firmware/export/usb-tcc7xx.h b/firmware/export/usb-tcc7xx.h index dc091ad671..787977312f 100644 --- a/firmware/export/usb-tcc7xx.h +++ b/firmware/export/usb-tcc7xx.h | |||
@@ -44,6 +44,7 @@ | |||
44 | #define TCC7xx_USB_SYS_STAT_SUSPEND (1<<1) /* Host forced suspend */ | 44 | #define TCC7xx_USB_SYS_STAT_SUSPEND (1<<1) /* Host forced suspend */ |
45 | #define TCC7xx_USB_SYS_STAT_RESUME (1<<2) /* Host forced resume */ | 45 | #define TCC7xx_USB_SYS_STAT_RESUME (1<<2) /* Host forced resume */ |
46 | #define TCC7xx_USB_SYS_STAT_HIGH (1<<4) /* High speed */ | 46 | #define TCC7xx_USB_SYS_STAT_HIGH (1<<4) /* High speed */ |
47 | #define TCC7xx_USB_SYS_STAT_SPD_END (1<<6) /* Speed detection end */ | ||
47 | #define TCC7xx_USB_SYS_STAT_VBON (1<<8) | 48 | #define TCC7xx_USB_SYS_STAT_VBON (1<<8) |
48 | #define TCC7xx_USB_SYS_STAT_VBOF (1<<9) | 49 | #define TCC7xx_USB_SYS_STAT_VBOF (1<<9) |
49 | #define TCC7xx_USB_SYS_STAT_EOERR (1<<10) /* overrun error */ | 50 | #define TCC7xx_USB_SYS_STAT_EOERR (1<<10) /* overrun error */ |
@@ -85,9 +86,20 @@ | |||
85 | 86 | ||
86 | /* Indexed registers, write endpoint number to TCC7xx_USB_INDEX */ | 87 | /* Indexed registers, write endpoint number to TCC7xx_USB_INDEX */ |
87 | #define TCC7xx_USB_EP_STAT MMR_REG16(USB_BASE, 0x2c) /* EP status register */ | 88 | #define TCC7xx_USB_EP_STAT MMR_REG16(USB_BASE, 0x2c) /* EP status register */ |
89 | #define TCC7xx_USP_EP_STAT_RPS (1 << 0) /* Packet received */ | ||
90 | #define TCC7xx_USP_EP_STAT_TPS (1 << 1) /* Packet transmited */ | ||
91 | #define TCC7xx_USP_EP_STAT_LWO (1 << 4) /* Last word odd */ | ||
88 | #define TCC7xx_USB_EP_CTRL MMR_REG16(USB_BASE, 0x30) /* EP control register */ | 92 | #define TCC7xx_USB_EP_CTRL MMR_REG16(USB_BASE, 0x30) /* EP control register */ |
89 | #define TCC7xx_USB_EP_CTRL_CDP (1 << 2) /* Clear Data PID */ | 93 | #define TCC7xx_USB_EP_CTRL_TZLS (1 << 0) /* TX Zero Length Set */ |
90 | #define TCC7xx_USB_EP_CTRL_FLUSH (1 << 6) /* Flush FIFO */ | 94 | #define TCC7xx_USB_EP_CTRL_ESS (1 << 1) /* Endpoint Stall Set */ |
95 | #define TCC7xx_USB_EP_CTRL_CDP (1 << 2) /* Clear Data PID */ | ||
96 | #define TCC7xx_USB_EP_CTRL_TTE (1 << 5) /* TX Toggle Enable */ | ||
97 | #define TCC7xx_USB_EP_CTRL_FLUSH (1 << 6) /* Flush FIFO */ | ||
98 | #define TCC7xx_USB_EP_CTRL_DUEN (1 << 7) /* Dual FIFO Mode */ | ||
99 | #define TCC7xx_USB_EP_CTRL_IME (1 << 8) /* ISO Mode */ | ||
100 | #define TCC7xx_USB_EP_CTRL_OUTHD (1 << 11) /* OUT Packet Hold */ | ||
101 | #define TCC7xx_USB_EP_CTRL_INHLD (1 << 12) /* IN Packet Hold */ | ||
102 | |||
91 | #define TCC7xx_USB_EP_BRCR MMR_REG16(USB_BASE, 0x34) /* EP byte read count register */ | 103 | #define TCC7xx_USB_EP_BRCR MMR_REG16(USB_BASE, 0x34) /* EP byte read count register */ |
92 | #define TCC7xx_USB_EP_BWCR MMR_REG16(USB_BASE, 0x38) /* EP byte write count register */ | 104 | #define TCC7xx_USB_EP_BWCR MMR_REG16(USB_BASE, 0x38) /* EP byte write count register */ |
93 | #define TCC7xx_USB_EP_MAXP MMR_REG16(USB_BASE, 0x3c) /* EP max packet register */ | 105 | #define TCC7xx_USB_EP_MAXP MMR_REG16(USB_BASE, 0x3c) /* EP max packet register */ |