diff options
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 60 | ||||
-rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 17 |
2 files changed, 48 insertions, 29 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 282f6adda0..21a105732a 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -69,16 +69,22 @@ | |||
69 | #define AS3525_FCLK_PREDIV 0 | 69 | #define AS3525_FCLK_PREDIV 0 |
70 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ | 70 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ |
71 | 71 | ||
72 | /* XXX: CGU_PERI might also be different (i.e. no PCLK_DIV1_SEL), but if we use | 72 | /* XXX: CGU_PERI might also be different (i.e. no PCLK_DIV1_SEL), so we don't |
73 | * the same frequency for DRAM & PCLK it's not a problem as the bit is unset | 73 | * set bit 6 (PCLK_DIV1_SEL) for the moment |
74 | * | 74 | * |
75 | * Note that setting bits 1:0 have no effect and they always read back as 0 | 75 | * Note that setting bits 1:0 have no effect and they always read back as 0 |
76 | * Perhaps it means CGU_PERI defaults to PLLA as source ? | 76 | * Also note that CGU_PERI is based on fclk, not PLLA |
77 | */ | 77 | */ |
78 | |||
79 | #ifdef SANSA_FUZEV2 | ||
80 | /* XXX: display is noticeably slower at 24MHz */ | ||
78 | #define AS3525_DRAM_FREQ 60000000 /* Initial DRAM frequency */ | 81 | #define AS3525_DRAM_FREQ 60000000 /* Initial DRAM frequency */ |
79 | #define AS3525_PCLK_FREQ AS3525_DRAM_FREQ/1 | 82 | #else |
83 | #define AS3525_DRAM_FREQ 24000000 /* Initial DRAM frequency */ | ||
84 | #endif /* SANSA_FUZEV2 */ | ||
80 | 85 | ||
81 | #else /* AS3525v1 */ | 86 | #else |
87 | /* AS3525v1 */ | ||
82 | 88 | ||
83 | /* PLL frequencies and settings*/ | 89 | /* PLL frequencies and settings*/ |
84 | #define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */ | 90 | #define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */ |
@@ -102,42 +108,31 @@ | |||
102 | 108 | ||
103 | #define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ | 109 | #define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ |
104 | #define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ | 110 | #define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ |
105 | /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ | 111 | /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ |
106 | #define AS3525_PCLK_FREQ AS3525_DRAM_FREQ/1 /* PCLK divided from DRAM freq */ | ||
107 | 112 | ||
108 | #endif /* CONFIG_CPU == AS3525v2 */ | 113 | #endif /* CONFIG_CPU == AS3525v2 */ |
109 | 114 | ||
110 | #define AS3525_DBOP_FREQ AS3525_PCLK_FREQ/1 /* DBOP divided from PCLK freq */ | 115 | #define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ |
111 | 116 | ||
112 | /** ****************************************************************************/ | 117 | #define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */ |
113 | 118 | ||
114 | /* Figure out if we need to use asynchronous bus */ | 119 | /** ****************************************************************************/ |
115 | #if (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ) | ||
116 | #define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */ | ||
117 | #endif | ||
118 | 120 | ||
119 | /* Tell the software what frequencies we're running */ | 121 | /* Tell the software what frequencies we're running */ |
120 | #define CPUFREQ_MAX AS3525_FCLK_FREQ | 122 | #define CPUFREQ_MAX AS3525_FCLK_FREQ |
121 | |||
122 | #if CONFIG_CPU == AS3525 | ||
123 | #define CPUFREQ_DEFAULT AS3525_PCLK_FREQ | 123 | #define CPUFREQ_DEFAULT AS3525_PCLK_FREQ |
124 | #define CPUFREQ_NORMAL AS3525_PCLK_FREQ | 124 | #define CPUFREQ_NORMAL AS3525_PCLK_FREQ |
125 | #else | ||
126 | /* On as3525v2, pclk & fclk are not bound */ | ||
127 | #ifdef SANSA_FUZEV2 | ||
128 | /* scrollwheel is much less responsive under 60MHz */ | ||
129 | #define CPUFREQ_DEFAULT 60000000 | ||
130 | #define CPUFREQ_NORMAL 60000000 | ||
131 | #else | ||
132 | #define CPUFREQ_DEFAULT 24000000 | ||
133 | #define CPUFREQ_NORMAL 24000000 | ||
134 | #endif /* SANSA_FUZEV2 */ | ||
135 | #endif /* CONFIG_CPU == AS3525 */ | ||
136 | 125 | ||
137 | /* FCLK */ | 126 | /* FCLK */ |
138 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA | 127 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA |
139 | #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ | 128 | #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ |
140 | #define AS3525_FCLK_POSTDIV_UNBOOSTED (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) : needed for as3525v2 */ | 129 | |
130 | #if CONFIG_CPU == AS3525v2 | ||
131 | /* On as3525v2 we change fclk by writing to CGU_PROC */ | ||
132 | #define AS3525_FCLK_POSTDIV_UNBOOSTED (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) */ | ||
133 | /* Since pclk is based on fclk, we need to change CGU_PERI as well */ | ||
134 | #define AS3525_PCLK_DIV0_UNBOOSTED (CLK_DIV(CPUFREQ_NORMAL, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ | ||
135 | #endif /* CONFIG_CPU == AS3525v2 */ | ||
141 | 136 | ||
142 | /* MCLK */ | 137 | /* MCLK */ |
143 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA | 138 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA |
@@ -150,13 +145,20 @@ | |||
150 | #endif | 145 | #endif |
151 | 146 | ||
152 | /* PCLK */ | 147 | /* PCLK */ |
148 | |||
149 | /* Figure out if we need to use asynchronous bus */ | ||
150 | #if ((CONFIG_CPU == AS3525) && (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ)) | ||
151 | #define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */ | ||
152 | #endif | ||
153 | |||
153 | #ifdef ASYNCHRONOUS_BUS | 154 | #ifdef ASYNCHRONOUS_BUS |
154 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ | 155 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ |
155 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/ | 156 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/ |
156 | #else | 157 | #else /* ASYNCHRONOUS_BUS */ |
157 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */ | 158 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */ |
158 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ | 159 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ |
159 | #endif | 160 | #endif /* ASYNCHRONOUS_BUS */ |
161 | |||
160 | /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ | 162 | /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ |
161 | #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ | 163 | #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ |
162 | 164 | ||
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 0d91d9cad4..feaf06aab1 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c | |||
@@ -290,7 +290,9 @@ void system_init(void) | |||
290 | /* Set PCLK frequency */ | 290 | /* Set PCLK frequency */ |
291 | CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ | 291 | CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ |
292 | (AS3525_PCLK_DIV0 << 2) | | 292 | (AS3525_PCLK_DIV0 << 2) | |
293 | #if CONFIG_CPU == AS3525 | ||
293 | (AS3525_PCLK_DIV1 << 6) | | 294 | (AS3525_PCLK_DIV1 << 6) | |
295 | #endif | ||
294 | AS3525_PCLK_SEL); | 296 | AS3525_PCLK_SEL); |
295 | 297 | ||
296 | #ifdef BOOTLOADER | 298 | #ifdef BOOTLOADER |
@@ -372,9 +374,16 @@ void set_cpu_frequency(long frequency) | |||
372 | "mcr p15, 0, r0, c1, c0 \n" | 374 | "mcr p15, 0, r0, c1, c0 \n" |
373 | : : : "r0" ); | 375 | : : : "r0" ); |
374 | #else | 376 | #else |
377 | /* AS3525v2 */ | ||
378 | int oldstatus = disable_irq_save(); | ||
379 | |||
380 | /* Change PCLK while FCLK is low, so it doesn't go too high */ | ||
381 | CGU_PERI = (CGU_PERI & ~(0x1F << 2)) | (AS3525_PCLK_DIV0 << 2); | ||
382 | |||
375 | CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | | 383 | CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | |
376 | (AS3525_FCLK_PREDIV << 2) | | 384 | (AS3525_FCLK_PREDIV << 2) | |
377 | AS3525_FCLK_SEL); | 385 | AS3525_FCLK_SEL); |
386 | restore_irq(oldstatus); | ||
378 | #endif /* CONFIG_CPU == AS3525 */ | 387 | #endif /* CONFIG_CPU == AS3525 */ |
379 | 388 | ||
380 | cpu_frequency = CPUFREQ_MAX; | 389 | cpu_frequency = CPUFREQ_MAX; |
@@ -388,9 +397,17 @@ void set_cpu_frequency(long frequency) | |||
388 | "mcr p15, 0, r0, c1, c0 \n" | 397 | "mcr p15, 0, r0, c1, c0 \n" |
389 | : : : "r0" ); | 398 | : : : "r0" ); |
390 | #else | 399 | #else |
400 | /* AS3525v2 */ | ||
401 | int oldstatus = disable_irq_save(); | ||
402 | |||
391 | CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) | | 403 | CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) | |
392 | (AS3525_FCLK_PREDIV << 2) | | 404 | (AS3525_FCLK_PREDIV << 2) | |
393 | AS3525_FCLK_SEL); | 405 | AS3525_FCLK_SEL); |
406 | |||
407 | /* Change PCLK after FCLK is low, so it doesn't go too high */ | ||
408 | CGU_PERI = (CGU_PERI & ~(0x1F << 2)) | (AS3525_PCLK_DIV0_UNBOOSTED << 2); | ||
409 | |||
410 | restore_irq(oldstatus); | ||
394 | #endif /* CONFIG_CPU == AS3525 */ | 411 | #endif /* CONFIG_CPU == AS3525 */ |
395 | 412 | ||
396 | #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE | 413 | #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE |