3 files changed, 33 insertions, 2 deletions

diff --git a/firmware/export/config-gigabeat.h b/firmware/export/config-gigabeat.h
index a12322ef4c..6e22e8d7ab 100644
--- a/firmware/export/config-gigabeat.h
+++ b/firmware/export/config-gigabeat.h
@@ -124,10 +124,9 @@
 #define USB_GIGABEAT_STYLE
 
 #define HAVE_HEADPHONE_DETECTION
+
 /* Define this if you have adjustable CPU frequency */
-#if 0 /* TODO */
 #define HAVE_ADJUSTABLE_CPU_FREQ
-#endif
 
 #define BOOTFILE_EXT "gigabeat"
 #define BOOTFILE "rockbox." BOOTFILE_EXT
diff --git a/firmware/export/system.h b/firmware/export/system.h
index 86bbefb28f..688cf9bc15 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -273,6 +273,14 @@ static inline unsigned long swap32(unsigned long value)
 
 /* TODO: Implement set_irq_level and check CPU frequencies */
 
+#if CONFIG_CPU == S3C2440
+
+#define CPUFREQ_DEFAULT 98784000
+#define CPUFREQ_NORMAL  98784000
+#define CPUFREQ_MAX    296352000
+
+#else
+
 #define CPUFREQ_DEFAULT_MULT 8
 #define CPUFREQ_DEFAULT 24000000
 #define CPUFREQ_NORMAL_MULT 10
@@ -280,6 +288,8 @@ static inline unsigned long swap32(unsigned long value)
 #define CPUFREQ_MAX_MULT 25
 #define CPUFREQ_MAX 75000000
 
+#endif
+
 static inline unsigned short swap16(unsigned short value)
     /*
       result[15..8] = value[ 7..0];
diff --git a/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c b/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c
index b922daaaa0..0cb16668f3 100644
--- a/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c
+++ b/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c
@@ -68,4 +68,26 @@ void system_init(void)
     
 }
 
+void set_cpu_frequency(long frequency)
+{
+    if (frequency == CPUFREQ_MAX)
+    {
+        /* FCLK: 300MHz, HCLK: 100MHz, PCLK: 50MHz */
+        /* MDIV: 97, PDIV: 1, SDIV: 2 */
+        /* HDIV: 3, PDIV: 1 */
+
+        MPLLCON = (97 << 12) | (1 << 4) | 2;
+        CLKDIVN = (3 << 1) | 1;
+        FREQ = CPUFREQ_MAX;
+    }
+    else
+    {
+        /* FCLK: 200MHz, HCLK: 100MHz, PCLK: 50MHz */
+        /* MDIV: 62, PDIV: 1, SDIV: 2 */
+        /* HDIV: 1, PDIV: 1 */
 
+        MPLLCON = (62 << 12) | (1 << 4) | 3;
+        CLKDIVN = (0 << 1) | 1;
+        FREQ = CPUFREQ_NORMAL;
+    }
+}