diff options
-rw-r--r-- | firmware/drivers/audio/uda1380.c | 48 |
1 files changed, 40 insertions, 8 deletions
diff --git a/firmware/drivers/audio/uda1380.c b/firmware/drivers/audio/uda1380.c index 2fe562f865..156eb822b6 100644 --- a/firmware/drivers/audio/uda1380.c +++ b/firmware/drivers/audio/uda1380.c | |||
@@ -76,18 +76,34 @@ static unsigned short uda1380_regs[0x30]; | |||
76 | static short recgain_mic; | 76 | static short recgain_mic; |
77 | static short recgain_line; | 77 | static short recgain_line; |
78 | 78 | ||
79 | #ifdef USE_WSPLL | ||
80 | |||
81 | /* Internal control of WSPLL */ | ||
82 | static bool wspll_enable = false; | ||
83 | |||
84 | static void wspll_on(bool on) | ||
85 | { | ||
86 | uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK); | ||
87 | uda1380_regs[REG_PWR] &= ~PON_PLL; | ||
88 | |||
89 | unsigned short pll_ena = (on) ? (ADC_CLK | DAC_CLK) : 0; | ||
90 | unsigned short pll_pow = (on) ? PON_PLL : 0; | ||
91 | |||
92 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | pll_ena); | ||
93 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | pll_pow); | ||
94 | |||
95 | wspll_enable = on; | ||
96 | } | ||
97 | #endif | ||
98 | |||
79 | /* Definition of a playback configuration to start with */ | 99 | /* Definition of a playback configuration to start with */ |
80 | 100 | ||
81 | #define NUM_DEFAULT_REGS 13 | 101 | #define NUM_DEFAULT_REGS 13 |
82 | static const unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] = | 102 | static const unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] = |
83 | { | 103 | { |
84 | REG_0, EN_DAC | EN_INT | EN_DEC | | 104 | REG_0, EN_DAC | EN_INT | EN_DEC | WSPLL_25_50 | SYSCLK_256FS, |
85 | #ifdef USE_WSPLL | ||
86 | ADC_CLK | DAC_CLK | WSPLL_25_50 | | ||
87 | #endif | ||
88 | SYSCLK_256FS, | ||
89 | REG_I2S, I2S_IFMT_IIS, | 105 | REG_I2S, I2S_IFMT_IIS, |
90 | REG_PWR, PON_PLL | PON_BIAS, | 106 | REG_PWR, PON_BIAS, |
91 | /* PON_HP & PON_DAC is enabled later */ | 107 | /* PON_HP & PON_DAC is enabled later */ |
92 | REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f), | 108 | REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f), |
93 | /* 00=max, 3f=mute */ | 109 | /* 00=max, 3f=mute */ |
@@ -225,6 +241,22 @@ void audiohw_set_frequency(int fsel) | |||
225 | 241 | ||
226 | ent = values_reg[fsel]; | 242 | ent = values_reg[fsel]; |
227 | 243 | ||
244 | #ifdef USE_WSPLL | ||
245 | /* Enable WSPLL if needed (for Iriver H100 and H300 series) */ | ||
246 | if (fsel == HW_FREQ_88) | ||
247 | { | ||
248 | /* Only at this case we need use WSPLL on DAC part for Iriver H100 and H300 series, because Coldfire work | ||
249 | at 11289600 Hz frequency and SYSCLK of UDA1380 can only be 256fs, 384fs, 512fs and 768fs. But in this case SYSCLK | ||
250 | is 128fs : 11289600 / 88200 = 128 */ | ||
251 | if (!wspll_enable) wspll_on(true); | ||
252 | } | ||
253 | else | ||
254 | { | ||
255 | /* At this case WSPLL clock and SYSCLK has same value and we don't use WSPLL to avoid WSPLL errors */ | ||
256 | if (wspll_enable) wspll_on(false); | ||
257 | } | ||
258 | #endif | ||
259 | |||
228 | /* Set WSPLL input frequency range or SYSCLK divider */ | 260 | /* Set WSPLL input frequency range or SYSCLK divider */ |
229 | uda1380_regs[REG_0] &= ~0xf; | 261 | uda1380_regs[REG_0] &= ~0xf; |
230 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ent[1]); | 262 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ent[1]); |
@@ -292,7 +324,7 @@ void audiohw_close(void) | |||
292 | void audiohw_enable_recording(bool source_mic) | 324 | void audiohw_enable_recording(bool source_mic) |
293 | { | 325 | { |
294 | #ifdef USE_WSPLL | 326 | #ifdef USE_WSPLL |
295 | uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK); | 327 | if (wspll_enable) uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK); |
296 | #endif | 328 | #endif |
297 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC); | 329 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC); |
298 | 330 | ||
@@ -339,7 +371,7 @@ void audiohw_disable_recording(void) | |||
339 | 371 | ||
340 | uda1380_regs[REG_0] &= ~EN_ADC; | 372 | uda1380_regs[REG_0] &= ~EN_ADC; |
341 | #ifdef USE_WSPLL | 373 | #ifdef USE_WSPLL |
342 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK); | 374 | if (wspll_enable) uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK); |
343 | #endif | 375 | #endif |
344 | 376 | ||
345 | uda1380_write_reg(REG_ADC, SKIP_DCFIL); | 377 | uda1380_write_reg(REG_ADC, SKIP_DCFIL); |