diff options
-rw-r--r-- | firmware/target/coldfire/iriver/system-iriver.c | 8 | ||||
-rw-r--r-- | firmware/target/coldfire/system-coldfire.c | 2 | ||||
-rw-r--r-- | firmware/target/coldfire/system-target.h | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index 43ba4eeed4..63011969b4 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c | |||
@@ -81,7 +81,7 @@ void set_cpu_frequency(long frequency) | |||
81 | PLLCR &= ~1; /* Bypass mode */ | 81 | PLLCR &= ~1; /* Bypass mode */ |
82 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 82 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
83 | RECALC_DELAYS(CPUFREQ_MAX); | 83 | RECALC_DELAYS(CPUFREQ_MAX); |
84 | PLLCR = 0x01056005 | (PLLCR & 0x70c00000); | 84 | PLLCR = 0x01856005 | (PLLCR & 0x70400000); |
85 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 85 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
86 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ | 86 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ |
87 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 87 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
@@ -108,7 +108,7 @@ void set_cpu_frequency(long frequency) | |||
108 | PLLCR &= ~1; /* Bypass mode */ | 108 | PLLCR &= ~1; /* Bypass mode */ |
109 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 109 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
110 | RECALC_DELAYS(CPUFREQ_NORMAL); | 110 | RECALC_DELAYS(CPUFREQ_NORMAL); |
111 | PLLCR = 0x0305e005 | (PLLCR & 0x70c00000); | 111 | PLLCR = 0x0385e005 | (PLLCR & 0x70400000); |
112 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 112 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
113 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 113 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
114 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 114 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
@@ -134,8 +134,8 @@ void set_cpu_frequency(long frequency) | |||
134 | PLLCR &= ~1; /* Bypass mode */ | 134 | PLLCR &= ~1; /* Bypass mode */ |
135 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); | 135 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); |
136 | RECALC_DELAYS(CPUFREQ_DEFAULT); | 136 | RECALC_DELAYS(CPUFREQ_DEFAULT); |
137 | /* Power down PLL, but keep CLSEL and CRSEL */ | 137 | /* Power down PLL, but keep CLSEL */ |
138 | PLLCR = 0x00000200 | (PLLCR & 0x70c00000); | 138 | PLLCR = 0x00000200 | (PLLCR & 0x70400000); |
139 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 139 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
140 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 140 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
141 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 141 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
diff --git a/firmware/target/coldfire/system-coldfire.c b/firmware/target/coldfire/system-coldfire.c index 2fc81496db..ff81d1cf39 100644 --- a/firmware/target/coldfire/system-coldfire.c +++ b/firmware/target/coldfire/system-coldfire.c | |||
@@ -314,6 +314,6 @@ int system_memory_guard(int newmode) | |||
314 | /* allow setting of audio clock related bits */ | 314 | /* allow setting of audio clock related bits */ |
315 | void coldfire_set_pllcr_audio_bits(long bits) | 315 | void coldfire_set_pllcr_audio_bits(long bits) |
316 | { | 316 | { |
317 | PLLCR = (PLLCR & ~0x70c00000) | (bits & 0x70c00000); | 317 | PLLCR = (PLLCR & ~0x70400000) | (bits & 0x70400000); |
318 | } | 318 | } |
319 | 319 | ||
diff --git a/firmware/target/coldfire/system-target.h b/firmware/target/coldfire/system-target.h index 24e3fb8705..183c38ba69 100644 --- a/firmware/target/coldfire/system-target.h +++ b/firmware/target/coldfire/system-target.h | |||
@@ -143,7 +143,7 @@ static inline void invalidate_icache(void) | |||
143 | #ifdef IAUDIO_X5 | 143 | #ifdef IAUDIO_X5 |
144 | #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000 | 144 | #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000 |
145 | #else | 145 | #else |
146 | #define DEFAULT_PLLCR_AUDIO_BITS 0x10c00000 | 146 | #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000 |
147 | #endif | 147 | #endif |
148 | void coldfire_set_pllcr_audio_bits(long bits); | 148 | void coldfire_set_pllcr_audio_bits(long bits); |
149 | 149 | ||