diff options
-rw-r--r-- | bootloader/x1000/utils.c | 10 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.c | 12 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.h | 20 |
3 files changed, 22 insertions, 20 deletions
diff --git a/bootloader/x1000/utils.c b/bootloader/x1000/utils.c index 5bad511b23..a2fd500f5d 100644 --- a/bootloader/x1000/utils.c +++ b/bootloader/x1000/utils.c | |||
@@ -375,22 +375,22 @@ static void probe_flash(int log_fd) | |||
375 | mdelay(10); | 375 | mdelay(10); |
376 | 376 | ||
377 | /* Try various read ID commands (cf. Linux's SPI NAND identify routine) */ | 377 | /* Try various read ID commands (cf. Linux's SPI NAND identify routine) */ |
378 | sfc_exec(NANDCMD_READID(0, 0), 0, buffer, readid_len|SFC_READ); | 378 | sfc_exec(NANDCMD_READID_OPCODE, 0, buffer, readid_len|SFC_READ); |
379 | fdprintf(log_fd, "readID opcode = %02x %02x %02x %02x\n", | 379 | fdprintf(log_fd, "readID opcode = %02x %02x %02x %02x\n", |
380 | buffer[0], buffer[1], buffer[2], buffer[3]); | 380 | buffer[0], buffer[1], buffer[2], buffer[3]); |
381 | 381 | ||
382 | sfc_exec(NANDCMD_READID(1, 0), 0, buffer, readid_len|SFC_READ); | 382 | sfc_exec(NANDCMD_READID_ADDR, 0, buffer, readid_len|SFC_READ); |
383 | fdprintf(log_fd, "readID address = %02x %02x %02x %02x\n", | 383 | fdprintf(log_fd, "readID address = %02x %02x %02x %02x\n", |
384 | buffer[0], buffer[1], buffer[2], buffer[3]); | 384 | buffer[0], buffer[1], buffer[2], buffer[3]); |
385 | 385 | ||
386 | sfc_exec(NANDCMD_READID(0, 8), 0, buffer, readid_len|SFC_READ); | 386 | sfc_exec(NANDCMD_READID_DUMMY, 0, buffer, readid_len|SFC_READ); |
387 | fdprintf(log_fd, "readID dummy = %02x %02x %02x %02x\n", | 387 | fdprintf(log_fd, "readID dummy = %02x %02x %02x %02x\n", |
388 | buffer[0], buffer[1], buffer[2], buffer[3]); | 388 | buffer[0], buffer[1], buffer[2], buffer[3]); |
389 | 389 | ||
390 | /* Try reading Ingenic SFC boot block */ | 390 | /* Try reading Ingenic SFC boot block */ |
391 | sfc_exec(NANDCMD_PAGE_READ(3), 0, NULL, 0); | 391 | sfc_exec(NANDCMD_PAGE_READ, 0, NULL, 0); |
392 | mdelay(500); | 392 | mdelay(500); |
393 | sfc_exec(NANDCMD_READ_CACHE_SLOW(2), 0, buffer, 16|SFC_READ); | 393 | sfc_exec(NANDCMD_READ_CACHE_SLOW, 0, buffer, 16|SFC_READ); |
394 | 394 | ||
395 | fdprintf(log_fd, "sfc params0 = %02x %02x %02x %02x\n", | 395 | fdprintf(log_fd, "sfc params0 = %02x %02x %02x %02x\n", |
396 | buffer[ 0], buffer[ 1], buffer[ 2], buffer[ 3]); | 396 | buffer[ 0], buffer[ 1], buffer[ 2], buffer[ 3]); |
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index 896ac97d28..827a79ebce 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
@@ -44,11 +44,11 @@ const struct nand_chip supported_nand_chips[] = { | |||
44 | STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS), | 44 | STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS), |
45 | SMP_DELAY(1)), | 45 | SMP_DELAY(1)), |
46 | .flags = NAND_CHIPFLAG_QUAD | NAND_CHIPFLAG_HAS_QE_BIT, | 46 | .flags = NAND_CHIPFLAG_QUAD | NAND_CHIPFLAG_HAS_QE_BIT, |
47 | .cmd_page_read = NANDCMD_PAGE_READ(3), | 47 | .cmd_page_read = NANDCMD_PAGE_READ, |
48 | .cmd_program_execute = NANDCMD_PROGRAM_EXECUTE(3), | 48 | .cmd_program_execute = NANDCMD_PROGRAM_EXECUTE, |
49 | .cmd_block_erase = NANDCMD_BLOCK_ERASE(3), | 49 | .cmd_block_erase = NANDCMD_BLOCK_ERASE, |
50 | .cmd_read_cache = NANDCMD_READ_CACHE_x4(2), | 50 | .cmd_read_cache = NANDCMD_READ_CACHE_x4, |
51 | .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4(2), | 51 | .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4, |
52 | }, | 52 | }, |
53 | #else | 53 | #else |
54 | { 0 }, | 54 | { 0 }, |
@@ -103,7 +103,7 @@ static bool identify_chip(struct nand_drv* drv) | |||
103 | * | 103 | * |
104 | * Currently we use the 2nd method, aka. address read ID. | 104 | * Currently we use the 2nd method, aka. address read ID. |
105 | */ | 105 | */ |
106 | sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 4|SFC_READ); | 106 | sfc_exec(NANDCMD_READID_ADDR, 0, drv->scratch_buf, 4|SFC_READ); |
107 | drv->mf_id = drv->scratch_buf[0]; | 107 | drv->mf_id = drv->scratch_buf[0]; |
108 | drv->dev_id = drv->scratch_buf[1]; | 108 | drv->dev_id = drv->scratch_buf[1]; |
109 | drv->dev_id2 = drv->scratch_buf[2]; | 109 | drv->dev_id2 = drv->scratch_buf[2]; |
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.h b/firmware/target/mips/ingenic_x1000/nand-x1000.h index b2bf4da358..227c71e3f4 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.h +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.h | |||
@@ -49,18 +49,20 @@ | |||
49 | 49 | ||
50 | /* cmd mode a d phase format has data */ | 50 | /* cmd mode a d phase format has data */ |
51 | #define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) | 51 | #define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) |
52 | #define NANDCMD_READID(x,y) SFC_CMD(0x9f, SFC_TMODE_1_1_1, x, y, SFC_PFMT_ADDR_FIRST, 1) | 52 | #define NANDCMD_READID_OPCODE SFC_CMD(0x9f, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 1) |
53 | #define NANDCMD_READID_ADDR SFC_CMD(0x9f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1) | ||
54 | #define NANDCMD_READID_DUMMY SFC_CMD(0x9f, SFC_TMODE_1_1_1, 0, 8, SFC_PFMT_ADDR_FIRST, 1) | ||
53 | #define NANDCMD_WR_EN SFC_CMD(0x06, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) | 55 | #define NANDCMD_WR_EN SFC_CMD(0x06, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) |
54 | #define NANDCMD_GET_FEATURE SFC_CMD(0x0f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1) | 56 | #define NANDCMD_GET_FEATURE SFC_CMD(0x0f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1) |
55 | #define NANDCMD_SET_FEATURE SFC_CMD(0x1f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1) | 57 | #define NANDCMD_SET_FEATURE SFC_CMD(0x1f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1) |
56 | #define NANDCMD_PAGE_READ(x) SFC_CMD(0x13, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0) | 58 | #define NANDCMD_PAGE_READ SFC_CMD(0x13, SFC_TMODE_1_1_1, 3, 0, SFC_PFMT_ADDR_FIRST, 0) |
57 | #define NANDCMD_READ_CACHE_SLOW(x) SFC_CMD(0x03, SFC_TMODE_1_1_1, x, 8, SFC_PFMT_ADDR_FIRST, 1) | 59 | #define NANDCMD_READ_CACHE_SLOW SFC_CMD(0x03, SFC_TMODE_1_1_1, 2, 8, SFC_PFMT_ADDR_FIRST, 1) |
58 | #define NANDCMD_READ_CACHE(x) SFC_CMD(0x0b, SFC_TMODE_1_1_1, x, 8, SFC_PFMT_ADDR_FIRST, 1) | 60 | #define NANDCMD_READ_CACHE SFC_CMD(0x0b, SFC_TMODE_1_1_1, 2, 8, SFC_PFMT_ADDR_FIRST, 1) |
59 | #define NANDCMD_READ_CACHE_x4(x) SFC_CMD(0x6b, SFC_TMODE_1_1_4, x, 8, SFC_PFMT_ADDR_FIRST, 1) | 61 | #define NANDCMD_READ_CACHE_x4 SFC_CMD(0x6b, SFC_TMODE_1_1_4, 2, 8, SFC_PFMT_ADDR_FIRST, 1) |
60 | #define NANDCMD_PROGRAM_LOAD(x) SFC_CMD(0x02, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 1) | 62 | #define NANDCMD_PROGRAM_EXECUTE SFC_CMD(0x10, SFC_TMODE_1_1_1, 3, 0, SFC_PFMT_ADDR_FIRST, 0) |
61 | #define NANDCMD_PROGRAM_LOAD_x4(x) SFC_CMD(0x32, SFC_TMODE_1_1_4, x, 0, SFC_PFMT_ADDR_FIRST, 1) | 63 | #define NANDCMD_PROGRAM_LOAD SFC_CMD(0x02, SFC_TMODE_1_1_1, 2, 0, SFC_PFMT_ADDR_FIRST, 1) |
62 | #define NANDCMD_PROGRAM_EXECUTE(x) SFC_CMD(0x10, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0) | 64 | #define NANDCMD_PROGRAM_LOAD_x4 SFC_CMD(0x32, SFC_TMODE_1_1_4, 2, 0, SFC_PFMT_ADDR_FIRST, 1) |
63 | #define NANDCMD_BLOCK_ERASE(x) SFC_CMD(0xd8, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0) | 65 | #define NANDCMD_BLOCK_ERASE SFC_CMD(0xd8, SFC_TMODE_1_1_1, 3, 0, SFC_PFMT_ADDR_FIRST, 0) |
64 | 66 | ||
65 | /* Feature registers are found in linux/mtd/spinand.h, | 67 | /* Feature registers are found in linux/mtd/spinand.h, |
66 | * apparently these are pretty standardized */ | 68 | * apparently these are pretty standardized */ |