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-rw-r--r--firmware/SOURCES2
-rw-r--r--firmware/drivers/arcotg_udc.c135
-rw-r--r--firmware/export/arcotg_udc.h (renamed from firmware/export/mx31.h)174
-rw-r--r--firmware/export/pp5020.h3
-rw-r--r--firmware/target/arm/usb-pp.c103
5 files changed, 217 insertions, 200 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index d4447c22cc..9842689544 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -212,6 +212,8 @@ drivers/tlv320.c
212drivers/isp1362.c 212drivers/isp1362.c
213#elif CONFIG_USBOTG == USBOTG_M5636 213#elif CONFIG_USBOTG == USBOTG_M5636
214drivers/m5636.c 214drivers/m5636.c
215#elif CONFIG_USBOTG == USBOTG_ARC
216drivers/arcotg_udc.c
215#endif /* CONFIG_USBOTG */ 217#endif /* CONFIG_USBOTG */
216#endif /* !defined(SIMULATOR) && !defined(BOOTLOADER) */ 218#endif /* !defined(SIMULATOR) && !defined(BOOTLOADER) */
217 219
diff --git a/firmware/drivers/arcotg_udc.c b/firmware/drivers/arcotg_udc.c
new file mode 100644
index 0000000000..d39dbc39df
--- /dev/null
+++ b/firmware/drivers/arcotg_udc.c
@@ -0,0 +1,135 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2007 by Barry Wardell
11 *
12 * Based on code from the Linux Target Image Builder from Freescale
13 * available at http://www.bitshrine.org/ and
14 * http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch
15 * Adapted for Rockbox in January 2007
16 * Original file: drivers/usb/gadget/arcotg_udc.c
17 *
18 * USB Device Controller Driver
19 * Driver for ARC OTG USB module in the i.MX31 platform, etc.
20 *
21 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
22 *
23 * Based on mpc-udc.h
24 * Author: Li Yang (leoli@freescale.com)
25 * Jiang Bo (Tanya.jiang@freescale.com)
26 *
27 * All files in this archive are subject to the GNU General Public License.
28 * See the file COPYING in the source tree root for full license agreement.
29 *
30 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
31 * KIND, either express or implied.
32 *
33 ****************************************************************************/
34#include "arcotg_udc.h"
35#include "logf.h"
36
37static int timeout;
38
39/* @qh_addr is the aligned virt addr of ep QH addr
40 * it is used to set endpointlistaddr Reg */
41/* was static int dr_controller_setup(void *qh_addr) */
42int dr_controller_setup(void)
43{
44#if 0
45 struct arc_usb_config *config;
46
47 config = udc_controller->config;
48
49 /* before here, make sure usb_slave_regs has been initialized */
50 if (!qh_addr)
51 return -EINVAL;
52#endif
53
54 /* Stop and reset the usb controller */
55 UDC_USBCMD &= ~USB_CMD_RUN_STOP;
56
57 UDC_USBCMD |= USB_CMD_CTRL_RESET;
58
59 /* Wait for reset to complete */
60 timeout = 10000000;
61 while ((UDC_USBCMD & USB_CMD_CTRL_RESET) &&
62 --timeout) {
63 continue;
64 }
65 if (timeout == 0) {
66 logf("%s: TIMEOUT", __FUNCTION__);
67 return -ETIMEDOUT;
68 }
69
70 /* Set the controller as device mode and disable setup lockout */
71 UDC_USBMODE |= (USB_MODE_CTRL_MODE_DEVICE | USB_MODE_SETUP_LOCK_OFF);
72
73 /* Clear the setup status */
74 UDC_USBSTS = 0;
75#if 0
76 UDC_ENDPOINTLISTADDR = (unsigned int)qh_addr & USB_EP_LIST_ADDRESS_MASK;
77
78 VDBG("qh_addr=0x%x epla_reg=0x%8x", qh_addr, UOG_ASYNCLISTADDR);
79#endif
80 UDC_PORTSC1 = (UDC_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | PORTSCX_PTS_UTMI;
81#if 0
82 if (config->set_vbus_power)
83 config->set_vbus_power(0);
84#endif
85
86 return 0;
87}
88
89/* just Enable DR irq reg and Set Dr controller Run */
90/* was static void dr_controller_run(struct arcotg_udc *udc) */
91void dr_controller_run(void)
92{
93 /*Enable DR irq reg */
94 UDC_USBINTR = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN |
95 USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN |
96 USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
97#if 0
98 /* Clear stopped bit */
99 udc->stopped = 0;
100#endif
101 /* Set the controller as device mode */
102 UDC_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
103
104 /* Set controller to Run */
105 UDC_USBCMD |= USB_CMD_RUN_STOP;
106
107 return;
108}
109
110/* just Enable DR irq reg and Set Dr controller Run */
111/* was static void dr_controller_stop(struct arcotg_udc *udc) */
112void dr_controller_stop(void)
113{
114#if 0
115 /* if we're in OTG mode, and the Host is currently using the port,
116 * stop now and don't rip the controller out from under the
117 * ehci driver
118 */
119 if (udc->gadget.is_otg) {
120 if (!(UDC_OTGSC & OTGSC_STS_USB_ID)) {
121 logf("Leaving early");
122 return;
123 }
124 }
125#endif
126
127 /* disable all INTR */
128 UDC_USBINTR = 0;
129#if 0
130 /* Set stopped bit */
131 udc->stopped = 1;
132#endif
133 /* Set controller to Stop */
134 UDC_USBCMD &= ~USB_CMD_RUN_STOP;
135}
diff --git a/firmware/export/mx31.h b/firmware/export/arcotg_udc.h
index 5af3bb052a..e3bf93a52e 100644
--- a/firmware/export/mx31.h
+++ b/firmware/export/arcotg_udc.h
@@ -5,12 +5,12 @@
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/ 7 * \/ \/ \/ \/ \/
8 * $Id: $ 8 * $Id$
9 * 9 *
10 * Copyright (C) 2007 by Barry Wardell 10 * Copyright (C) 2007 by Barry Wardell
11 * 11 *
12 * i.MX31 driver based on code from the Linux Target Image Builder from 12 * ARC OTG USB device driver based on code from the Linux Target Image Builder
13 * Freescale - http://www.bitshrine.org/ and 13 * from Freescale - http://www.bitshrine.org/ and
14 * http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch 14 * http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch
15 * Adapted for Rockbox in January 2007 15 * Adapted for Rockbox in January 2007
16 * Original file: drivers/usb/gadget/arcotg_udc.h 16 * Original file: drivers/usb/gadget/arcotg_udc.h
@@ -32,119 +32,62 @@
32/* 32/*
33 * Freescale USB device/endpoint management registers 33 * Freescale USB device/endpoint management registers
34 */ 34 */
35#ifndef __MX31_H 35#ifndef __ARCOTG_UDC_H
36#define __MX31_H 36#define __ARCOTG_UDC_H
37 37
38/* Register addresses - from Freescale i.MX31 reference manual */ 38#include "cpu.h"
39/* The PortalPlayer USB controller usec base address 0xc5000000 */ 39
40#define USB_BASE 0xc5000000 40#define ETIMEDOUT 1
41 41
42/* OTG */
43#define UOG_ID (*(volatile unsigned int *)(USB_BASE+0x000))
44#define UOG_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004))
45#define UOG_HWHOST (*(volatile unsigned int *)(USB_BASE+0x008))
46#define UOG_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x010))
47#define UOG_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x014))
48#define UOG_CAPLENGTH (*(volatile unsigned char *)(USB_BASE+0x100))
49#define UOG_HCIVERSION (*(volatile unsigned short *)(USB_BASE+0x102))
50#define UOG_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x104))
51#define UOG_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x108))
52#define UOG_DCIVERSION (*(volatile unsigned short *)(USB_BASE+0x120))
53#define UOG_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124))
54#define UOG_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140))
55#define UOG_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144))
56#define UOG_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148))
57#define UOG_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c))
58#define UOG_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x154))
59#define UOG_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
60#define UOG_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160))
61#define UOG_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x164))
62#define UOG_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x170))
63#define UOG_CFGFLAG (*(volatile unsigned int *)(USB_BASE+0x180))
64#define UOG_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184))
65/*#define UOG_PORTSC2 (*(volatile unsigned int *)(USB_BASE+0x188))
66#define UOG_PORTSC3 (*(volatile unsigned int *)(USB_BASE+0x18c))
67#define UOG_PORTSC4 (*(volatile unsigned int *)(USB_BASE+0x190))
68#define UOG_PORTSC5 (*(volatile unsigned int *)(USB_BASE+0x194))
69#define UOG_PORTSC6 (*(volatile unsigned int *)(USB_BASE+0x198))
70#define UOG_PORTSC7 (*(volatile unsigned int *)(USB_BASE+0x19c))
71#define UOG_PORTSC8 (*(volatile unsigned int *)(USB_BASE+0x1a0))*/
72#define UOG_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4))
73#define UOG_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8))
74#define UOG_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac))
75#define UOG_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0))
76#define UOG_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4))
77#define UOG_ENDPTSTAT (*(volatile unsigned int *)(USB_BASE+0x1b8))
78#define UOG_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc))
79#define ENDPTCRTL0 (*(volatile unsigned int *)(USB_BASE+0x1c0))
80#define ENDPTCRTL1 (*(volatile unsigned int *)(USB_BASE+0x1c4))
81#define ENDPTCRTL2 (*(volatile unsigned int *)(USB_BASE+0x1c8))
82#define ENDPTCRTL3 (*(volatile unsigned int *)(USB_BASE+0x1cc))
83#define ENDPTCRTL4 (*(volatile unsigned int *)(USB_BASE+0x1d0))
84#define ENDPTCRTL5 (*(volatile unsigned int *)(USB_BASE+0x1d4))
85#define ENDPTCRTL6 (*(volatile unsigned int *)(USB_BASE+0x1d8))
86#define ENDPTCRTL7 (*(volatile unsigned int *)(USB_BASE+0x1dc))
87/*#define ENDPTCRTL8 (*(volatile unsigned int *)(USB_BASE+0x1e0))
88#define ENDPTCRTL9 (*(volatile unsigned int *)(USB_BASE+0x1e4))
89#define ENDPTCRTL10 (*(volatile unsigned int *)(USB_BASE+0x1e8))
90#define ENDPTCRTL11 (*(volatile unsigned int *)(USB_BASE+0x1ec))
91#define ENDPTCRTL12 (*(volatile unsigned int *)(USB_BASE+0x1f0))
92#define ENDPTCRTL13 (*(volatile unsigned int *)(USB_BASE+0x1f4))
93#define ENDPTCRTL14 (*(volatile unsigned int *)(USB_BASE+0x1f8))
94#define ENDPTCRTL15 (*(volatile unsigned int *)(USB_BASE+0x1fc))*/
95
96/* Host 1 */
97#define UH1_ID (*(volatile unsigned int *)(USB_BASE+0x200))
98#define UH1_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x204))
99#define UH1_HWHOST (*(volatile unsigned int *)(USB_BASE+0x208))
100#define UH1_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x210))
101#define UH1_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x214))
102#define UH1_CAPLENGTH (*(volatile unsigned int *)(USB_BASE+0x300))
103#define UH1_HCIVERSION (*(volatile unsigned int *)(USB_BASE+0x302))
104#define UH1_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x304))
105#define UH1_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x308))
106#define UH1_USBCMD (*(volatile unsigned int *)(USB_BASE+0x340))
107#define UH1_USBSTS (*(volatile unsigned int *)(USB_BASE+0x344))
108#define UH1_USBINTR (*(volatile unsigned int *)(USB_BASE+0x348))
109#define UH1_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x34c))
110#define UH1_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x354))
111#define UH1_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x358))
112#define UH1_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x360))
113#define UH1_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x364))
114#define UH1_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x384))
115#define UH1_USBMODE (*(volatile unsigned int *)(USB_BASE+0x3a8))
116
117/* Host 2 */
118#define UH2_ID (*(volatile unsigned int *)(USB_BASE+0x400))
119#define UH2_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x404))
120#define UH2_HWHOST (*(volatile unsigned int *)(USB_BASE+0x408))
121#define UH2_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x410))
122#define UH2_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x414))
123#define UH2_CAPLENGTH (*(volatile unsigned int *)(USB_BASE+0x500))
124#define UH2_HCIVERSION (*(volatile unsigned int *)(USB_BASE+0x502))
125#define UH2_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x504))
126#define UH2_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x508))
127#define UH2_USBCMD (*(volatile unsigned int *)(USB_BASE+0x540))
128#define UH2_USBSTS (*(volatile unsigned int *)(USB_BASE+0x544))
129#define UH2_USBINTR (*(volatile unsigned int *)(USB_BASE+0x548))
130#define UH2_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x54c))
131#define UH2_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x554))
132#define UH2_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x558))
133#define UH2_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x560))
134#define UH2_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x564))
135#define UH2_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x570))
136#define UH2_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x584))
137#define UH2_USBMODE (*(volatile unsigned int *)(USB_BASE+0x5a8))
138
139/* General */
140#define USB_CTRL (*(volatile unsigned int *)(USB_BASE+0x600))
141#define USB_OTG_MIRROR (*(volatile unsigned int *)(USB_BASE+0x604))
142
143/* Maximum values */
144#define USB_MAX_ENDPOINTS 8 42#define USB_MAX_ENDPOINTS 8
145#define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2) 43#define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2)
146#define USB_MAX_CTRL_PAYLOAD 64 44#define USB_MAX_CTRL_PAYLOAD 64
147 45
46/* USB DR device mode registers (Little Endian) */
47/* Identification registers */
48#define UDC_ID (*(volatile unsigned int *)(USB_BASE+0x000))
49#define UDC_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004))
50#define UDC_HWHOST (*(volatile unsigned int *)(USB_BASE+0x008))
51#define UDC_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x010))
52#define UDC_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x014))
53
54/* Capability registers */
55#define UDC_CAPLENGTH (*(volatile unsigned char *)(USB_BASE+0x100)) /* Capability Register Length */
56#define UDC_HCIVERSION (*(volatile unsigned short *)(USB_BASE+0x102)) /* Host Controller Interface Version */
57#define UDC_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x104)) /* Host Controller Structual Parameters */
58#define UDC_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x108)) /* Host Controller Capability Parameters */
59#define UDC_DCIVERSION (*(volatile unsigned short *)(USB_BASE+0x120)) /* Device Controller Interface Version */
60#define UDC_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124)) /* Device Controller Capability Parameters */
61
62/* Operation registers */
63#define UDC_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140)) /* USB Command Register */
64#define UDC_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144)) /* USB Status Register */
65#define UDC_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148)) /* USB Interrupt Enable Register */
66#define UDC_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c)) /* Frame Index Register */
67#define UDC_DEVICEADDR (*(volatile unsigned int *)(USB_BASE+0x154)) /* Device Address */
68#define UDC_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158)) /* Endpoint List Address Register */
69#define UDC_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160)) /* Master Interface Data Burst Size Register */
70#define UDC_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x164)) /* Transmit FIFO Tuning Controls Register */
71#define UDC_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x170))
72#define UDC_CFGFLAG (*(volatile unsigned int *)(USB_BASE+0x180)) /* Configure Flag Register */
73#define UDC_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184)) /* Port 1 Status and Control Register */
74#define UDC_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4)) /* On-The-Go Status and Control */
75#define UDC_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8)) /* USB Mode Register */
76#define UDC_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac)) /* Endpoint Setup Status Register */
77#define UDC_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0)) /* Endpoint Initialization Register */
78#define UDC_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4)) /* Endpoint Flush Register */
79#define UDC_ENDPTSTAT (*(volatile unsigned int *)(USB_BASE+0x1b8)) /* Endpoint Status Register */
80#define UDC_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc)) /* Endpoint Complete Register */
81#define UDC_ENDPTCTRL0 (*(volatile unsigned int *)(USB_BASE+0x1c0)) /* Endpoint 0 Control Register */
82#define UDC_ENDPTCTRL1 (*(volatile unsigned int *)(USB_BASE+0x1c4)) /* Endpoint 1 Control Register */
83#define UDC_ENDPTCTRL2 (*(volatile unsigned int *)(USB_BASE+0x1c8)) /* Endpoint 2 Control Register */
84#define UDC_ENDPTCTRL3 (*(volatile unsigned int *)(USB_BASE+0x1cc)) /* Endpoint 3 Control Register */
85#define UDC_ENDPTCTRL4 (*(volatile unsigned int *)(USB_BASE+0x1d0)) /* Endpoint 4 Control Register */
86#define UDC_ENDPTCTRL5 (*(volatile unsigned int *)(USB_BASE+0x1d4)) /* Endpoint 5 Control Register */
87#define UDC_ENDPTCTRL6 (*(volatile unsigned int *)(USB_BASE+0x1d8)) /* Endpoint 6 Control Register */
88#define UDC_ENDPTCTRL7 (*(volatile unsigned int *)(USB_BASE+0x1dc)) /* Endpoint 7 Control Register */
89#define UDC_ENDPTCTRL(x) (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(x))) /* Endpoint X Control Register */
90
148/* ep0 transfer state */ 91/* ep0 transfer state */
149#define WAIT_FOR_SETUP 0 92#define WAIT_FOR_SETUP 0
150#define DATA_STATE_XMIT 1 93#define DATA_STATE_XMIT 1
@@ -369,4 +312,9 @@
369#define USB_CTRL_IOENB (0x00000004) 312#define USB_CTRL_IOENB (0x00000004)
370#define USB_CTRL_ULPI_INT0EN (0x00000001) 313#define USB_CTRL_ULPI_INT0EN (0x00000001)
371 314
372#endif /* __MX31_H */ 315/* Externally used functions */
316int dr_controller_setup(void);
317void dr_controller_run(void);
318void dr_controller_stop(void);
319
320#endif /* __ARCOTG_UDC_H */
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index 4e0e6eac2a..d30489526a 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -174,6 +174,9 @@
174#define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) 174#define IISFIFO_WR (*(volatile unsigned long*)(0x70002840))
175#define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) 175#define IISFIFO_RD (*(volatile unsigned long*)(0x70002880))
176 176
177/* The PortalPlayer USB controller uses base address 0xc5000000 */
178#define USB_BASE 0xc5000000
179
177#define PROC_SLEEP 0x80000000 180#define PROC_SLEEP 0x80000000
178#define PROC_WAKE 0x0 181#define PROC_WAKE 0x0
179 182
diff --git a/firmware/target/arm/usb-pp.c b/firmware/target/arm/usb-pp.c
index 983457b924..042fb5bda5 100644
--- a/firmware/target/arm/usb-pp.c
+++ b/firmware/target/arm/usb-pp.c
@@ -40,7 +40,7 @@
40#include "hwcompat.h" 40#include "hwcompat.h"
41 41
42#include "usb-target.h" 42#include "usb-target.h"
43#include "mx31.h" 43#include "arcotg_udc.h"
44 44
45void usb_init_device(void) 45void usb_init_device(void)
46{ 46{
@@ -56,30 +56,30 @@ void usb_init_device(void)
56 DEV_INIT |= INIT_USB; 56 DEV_INIT |= INIT_USB;
57 while ((inl(0x70000028) & 0x80) == 0); 57 while ((inl(0x70000028) & 0x80) == 0);
58 58
59 UOG_PORTSC1 |= PORTSCX_PORT_RESET; 59 UDC_PORTSC1 |= PORTSCX_PORT_RESET;
60 while ((UOG_PORTSC1 & PORTSCX_PORT_RESET) != 0); 60 while ((UDC_PORTSC1 & PORTSCX_PORT_RESET) != 0);
61 61
62 UOG_OTGSC |= 0x5F000000; 62 UDC_OTGSC |= 0x5F000000;
63 if( (UOG_OTGSC & 0x100) == 0) { 63 if( (UDC_OTGSC & 0x100) == 0) {
64 UOG_USBMODE &=~ USB_MODE_CTRL_MODE_HOST; 64 UDC_USBMODE &=~ USB_MODE_CTRL_MODE_HOST;
65 UOG_USBMODE |= USB_MODE_CTRL_MODE_DEVICE; 65 UDC_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
66 outl(inl(0x70000028) | 0x4000, 0x70000028); 66 outl(inl(0x70000028) | 0x4000, 0x70000028);
67 outl(inl(0x70000028) | 0x2, 0x70000028); 67 outl(inl(0x70000028) | 0x2, 0x70000028);
68 } else { 68 } else {
69 UOG_USBMODE |= USB_MODE_CTRL_MODE_DEVICE; 69 UDC_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
70 outl(inl(0x70000028) &~0x4000, 0x70000028); 70 outl(inl(0x70000028) &~0x4000, 0x70000028);
71 outl(inl(0x70000028) | 0x2, 0x70000028); 71 outl(inl(0x70000028) | 0x2, 0x70000028);
72 } 72 }
73 73
74 74
75 UOG_USBCMD |= USB_CMD_CTRL_RESET; 75 UDC_USBCMD |= USB_CMD_CTRL_RESET;
76 while((UOG_USBCMD & USB_CMD_CTRL_RESET) != 0); 76 while((UDC_USBCMD & USB_CMD_CTRL_RESET) != 0);
77 77
78 r0 = UOG_PORTSC1; 78 r0 = UDC_PORTSC1;
79 79
80 /* Note from IPL source (referring to next 5 lines of code: 80 /* Note from IPL source (referring to next 5 lines of code:
81 THIS NEEDS TO BE CHANGED ONCE THERE IS KERNEL USB */ 81 THIS NEEDS TO BE CHANGED ONCE THERE IS KERNEL USB */
82 outl(inl(0x70000020) | 0x80000000, 0x70000020); 82 DEV_INIT |= INIT_USB;
83 DEV_EN |= DEV_USB; 83 DEV_EN |= DEV_USB;
84 while ((inl(0x70000028) & 0x80) == 0); 84 while ((inl(0x70000028) & 0x80) == 0);
85 outl(inl(0x70000028) | 0x2, 0x70000028); 85 outl(inl(0x70000028) | 0x2, 0x70000028);
@@ -120,100 +120,29 @@ void usb_enable(bool on)
120 } 120 }
121} 121}
122 122
123/*------------------------------------------------------------------
124 Internal Hardware related function
125 ------------------------------------------------------------------*/
126
127/* @qh_addr is the aligned virt addr of ep QH addr
128 * it is used to set endpointlistaddr Reg */
129static int dr_controller_setup(void/* *qh_addr, struct device *dev*/)
130{
131 int timeout = 0;
132/* struct arc_usb_config *config;
133
134 config = udc_controller->config;
135*/
136 /* before here, make sure usb_slave_regs has been initialized */
137/* if (!qh_addr)
138 return -EINVAL;
139*/
140 /* Stop and reset the usb controller */
141 UOG_USBCMD &= ~USB_CMD_RUN_STOP;
142
143 UOG_USBCMD |= USB_CMD_CTRL_RESET;
144
145 /* Wait for reset to complete */
146 timeout = 10000000;
147 while ((UOG_USBCMD & USB_CMD_CTRL_RESET) &&
148 --timeout) {
149 continue;
150 }
151 if (timeout == 0) {
152 //logf("%s: TIMEOUT", __FUNCTION__);
153 return 1;
154 }
155
156 /* Set the controller as device mode and disable setup lockout */
157 UOG_USBMODE |= (USB_MODE_CTRL_MODE_DEVICE | USB_MODE_SETUP_LOCK_OFF);
158
159 /* Clear the setup status */
160 UOG_USBSTS = 0;
161
162/* tmp = virt_to_phys(qh_addr);
163 tmp &= USB_EP_LIST_ADDRESS_MASK;
164 usb_slave_regs->endpointlistaddr = cpu_to_le32(tmp);
165*/
166 UOG_PORTSC1 = (UOG_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | PORTSCX_PTS_UTMI;
167
168/* if (config->set_vbus_power)
169 config->set_vbus_power(0);
170*/
171 return 0;
172}
173
174/* just Enable DR irq reg and Set Dr controller Run */
175static void dr_controller_run(void/*struct arcotg_udc *udc*/)
176{
177 /*Enable DR irq reg */
178 UOG_USBINTR = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN |
179 USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN |
180 USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
181
182 /* Clear stopped bit */
183 /*udc->stopped = 0;*/
184
185 /* Set the controller as device mode */
186 UOG_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
187
188 /* Set controller to Run */
189 UOG_USBCMD |= USB_CMD_RUN_STOP;
190
191 return;
192}
193
194bool usb_detect(void) 123bool usb_detect(void)
195{ 124{
196 static bool prev_usbstatus1 = false; 125 static bool prev_usbstatus1 = false;
197 bool usbstatus1,usbstatus2; 126 bool usbstatus1,usbstatus2;
198 127
199 /* UOG_ID should have the bit format: 128 /* UDC_ID should have the bit format:
200 [31:24] = 0x0 129 [31:24] = 0x0
201 [23:16] = 0x22 (Revision number) 130 [23:16] = 0x22 (Revision number)
202 [15:14] = 0x3 (Reserved) 131 [15:14] = 0x3 (Reserved)
203 [13:8] = 0x3a (NID - 1's compliment of ID) 132 [13:8] = 0x3a (NID - 1's compliment of ID)
204 [7:6] = 0x0 (Reserved) 133 [7:6] = 0x0 (Reserved)
205 [5:0] = 0x05 (ID) */ 134 [5:0] = 0x05 (ID) */
206 if (UOG_ID != 0x22FA05) { 135 if (UDC_ID != 0x22FA05) {
207 return false; 136 return false;
208 } 137 }
209 138
210 usbstatus1 = (UOG_OTGSC & 0x800) ? true : false; 139 usbstatus1 = (UDC_OTGSC & 0x800) ? true : false;
211 if ((usbstatus1 == true) && (prev_usbstatus1 == false)) { 140 if ((usbstatus1 == true) && (prev_usbstatus1 == false)) {
212 dr_controller_setup(); 141 dr_controller_setup();
213 dr_controller_run(); 142 dr_controller_run();
214 } 143 }
215 prev_usbstatus1 = usbstatus1; 144 prev_usbstatus1 = usbstatus1;
216 usbstatus2 = (UOG_PORTSC1 & PORTSCX_CURRENT_CONNECT_STATUS) ? true : false; 145 usbstatus2 = (UDC_PORTSC1 & PORTSCX_CURRENT_CONNECT_STATUS) ? true : false;
217 146
218 if (usbstatus1 && usbstatus2) { 147 if (usbstatus1 && usbstatus2) {
219 return true; 148 return true;
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-03 09:18:07 +0000