diff options
-rw-r--r-- | firmware/export/pp5002.h | 7 | ||||
-rw-r--r-- | firmware/rolo.c | 17 | ||||
-rw-r--r-- | firmware/target/arm/crt0-pp-bl.S | 2 | ||||
-rw-r--r-- | firmware/target/arm/system-pp5002.c | 4 |
4 files changed, 17 insertions, 13 deletions
diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h index cdf0318e55..b0c31d9474 100644 --- a/firmware/export/pp5002.h +++ b/firmware/export/pp5002.h | |||
@@ -214,8 +214,9 @@ | |||
214 | 214 | ||
215 | /* Cache Control */ | 215 | /* Cache Control */ |
216 | #define CACHE_CTL (*(volatile unsigned long *)(0xcf004024)) | 216 | #define CACHE_CTL (*(volatile unsigned long *)(0xcf004024)) |
217 | #define CACHE_RUN 0x1 | 217 | #define CACHE_CTL_DISABLE 0x0 |
218 | #define CACHE_INIT 0x2 | 218 | #define CACHE_CTL_RUN 0x1 |
219 | #define CACHE_CTL_INIT 0x2 | ||
219 | 220 | ||
220 | #define CACHE_MASK (*(volatile unsigned long *)(0xf000f020)) | 221 | #define CACHE_MASK (*(volatile unsigned long *)(0xf000f020)) |
221 | #define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f024)) | 222 | #define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f024)) |
@@ -239,6 +240,8 @@ | |||
239 | #define PLL_MULT (*(volatile unsigned long *)(0xcf00501c)) | 240 | #define PLL_MULT (*(volatile unsigned long *)(0xcf00501c)) |
240 | #define PLL_UNLOCK (*(volatile unsigned long *)(0xcf005038)) | 241 | #define PLL_UNLOCK (*(volatile unsigned long *)(0xcf005038)) |
241 | 242 | ||
243 | #define MMAP_FIRST (*(volatile unsigned long *)(0xf000f000)) | ||
244 | #define MMAP_LAST (*(volatile unsigned long *)(0xf000f01c)) | ||
242 | #define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000)) | 245 | #define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000)) |
243 | #define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004)) | 246 | #define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004)) |
244 | #define MMAP1_LOGICAL (*(volatile unsigned long *)(0xf000f008)) | 247 | #define MMAP1_LOGICAL (*(volatile unsigned long *)(0xf000f008)) |
diff --git a/firmware/rolo.c b/firmware/rolo.c index 58404eecff..c7927978bd 100644 --- a/firmware/rolo.c +++ b/firmware/rolo.c | |||
@@ -44,9 +44,8 @@ | |||
44 | #define FIRMWARE_OFFSET_FILE_DATA 0x200 | 44 | #define FIRMWARE_OFFSET_FILE_DATA 0x200 |
45 | #endif | 45 | #endif |
46 | 46 | ||
47 | #if !defined(IRIVER_IFP7XX_SERIES) && \ | 47 | #if !defined(IRIVER_IFP7XX_SERIES) |
48 | (CONFIG_CPU != PP5002) | 48 | /* FIX: this doesn't work on iFP */ |
49 | /* FIX: this doesn't work on iFP, 3rd Gen ipods */ | ||
50 | 49 | ||
51 | #define IRQ0_EDGE_TRIGGER 0x80 | 50 | #define IRQ0_EDGE_TRIGGER 0x80 |
52 | 51 | ||
@@ -92,8 +91,9 @@ void rolo_restart_cop(void) | |||
92 | cpu_reply = 2; | 91 | cpu_reply = 2; |
93 | 92 | ||
94 | asm volatile( | 93 | asm volatile( |
95 | "mov r0, #0x10000000 \n" | 94 | "mov r0, %0 \n" |
96 | "mov pc, r0 \n" | 95 | "mov pc, r0 \n" |
96 | : : "I"(DRAM_START) | ||
97 | ); | 97 | ); |
98 | } | 98 | } |
99 | #endif /* NUM_CORES > 1 */ | 99 | #endif /* NUM_CORES > 1 */ |
@@ -144,7 +144,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest, | |||
144 | "jmp (%0) \n" | 144 | "jmp (%0) \n" |
145 | : : "a"(dest) | 145 | : : "a"(dest) |
146 | ); | 146 | ); |
147 | #elif defined(CPU_PP502x) | 147 | #elif defined(CPU_PP) |
148 | CPU_INT_DIS = -1; | 148 | CPU_INT_DIS = -1; |
149 | 149 | ||
150 | /* Flush cache */ | 150 | /* Flush cache */ |
@@ -169,8 +169,9 @@ void rolo_restart(const unsigned char* source, unsigned char* dest, | |||
169 | #endif | 169 | #endif |
170 | 170 | ||
171 | asm volatile( | 171 | asm volatile( |
172 | "mov r0, #0x10000000 \n" | 172 | "mov r0, %0 \n" |
173 | "mov pc, r0 \n" | 173 | "mov pc, r0 \n" |
174 | : : "I"(DRAM_START) | ||
174 | ); | 175 | ); |
175 | 176 | ||
176 | #elif defined(CPU_ARM) | 177 | #elif defined(CPU_ARM) |
diff --git a/firmware/target/arm/crt0-pp-bl.S b/firmware/target/arm/crt0-pp-bl.S index 85950bb257..1d2909e7f4 100644 --- a/firmware/target/arm/crt0-pp-bl.S +++ b/firmware/target/arm/crt0-pp-bl.S | |||
@@ -45,7 +45,7 @@ start: | |||
45 | .equ CPUSLEEPING, 0x8000 | 45 | .equ CPUSLEEPING, 0x8000 |
46 | .equ COPSLEEPING, 0x4000 | 46 | .equ COPSLEEPING, 0x4000 |
47 | .equ CACHE_CTRL, 0xcf004024 | 47 | .equ CACHE_CTRL, 0xcf004024 |
48 | .equ CACHE_ENAB, 0x2 /* Actually the CACHE_INIT flag */ | 48 | .equ CACHE_ENAB, 0x2 /* Actually the CACHE_CTL_INIT flag */ |
49 | #else | 49 | #else |
50 | .equ PROC_ID, 0x60000000 | 50 | .equ PROC_ID, 0x60000000 |
51 | .equ CPU_CTRL, 0x60007000 | 51 | .equ CPU_CTRL, 0x60007000 |
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c index 98bf5f21f1..976e5e585b 100644 --- a/firmware/target/arm/system-pp5002.c +++ b/firmware/target/arm/system-pp5002.c | |||
@@ -97,7 +97,7 @@ static void ipod_init_cache(void) | |||
97 | PROC_STAT &= ~0x700; | 97 | PROC_STAT &= ~0x700; |
98 | outl(0x4000, 0xcf004020); | 98 | outl(0x4000, 0xcf004020); |
99 | 99 | ||
100 | CACHE_CTL = CACHE_INIT; | 100 | CACHE_CTL = CACHE_CTL_INIT; |
101 | 101 | ||
102 | for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE; | 102 | for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE; |
103 | b < e; b += 16) { | 103 | b < e; b += 16) { |
@@ -113,7 +113,7 @@ static void ipod_init_cache(void) | |||
113 | CACHE_MASK = 0x00001c00; | 113 | CACHE_MASK = 0x00001c00; |
114 | CACHE_OPERATION = 0x3fc0; | 114 | CACHE_OPERATION = 0x3fc0; |
115 | 115 | ||
116 | CACHE_CTL = CACHE_INIT | CACHE_RUN; | 116 | CACHE_CTL = CACHE_CTL_INIT | CACHE_CTL_RUN; |
117 | } | 117 | } |
118 | 118 | ||
119 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 119 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |