diff options
4 files changed, 12 insertions, 29 deletions
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h index 26a8b840c9..1238d7e452 100644 --- a/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h | |||
@@ -25,11 +25,6 @@ | |||
25 | /* The max page size (main + spare) of all NAND chips used by this target */ | 25 | /* The max page size (main + spare) of all NAND chips used by this target */ |
26 | #define NAND_MAX_PAGE_SIZE (2048 + 64) | 26 | #define NAND_MAX_PAGE_SIZE (2048 + 64) |
27 | 27 | ||
28 | /* The clock source to use for the SFC controller. Note the SPL has special | ||
29 | * handling which ignores this choice, so it only applies to bootloader & app. | ||
30 | */ | ||
31 | #define NAND_CLOCK_SOURCE X1000_CLK_SCLK_A | ||
32 | |||
33 | /* The clock speed to use for the SFC controller during chip identification */ | 28 | /* The clock speed to use for the SFC controller during chip identification */ |
34 | #define NAND_INIT_CLOCK_SPEED 150000000 | 29 | #define NAND_INIT_CLOCK_SPEED 150000000 |
35 | 30 | ||
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index e6d5b6e4c7..fc8d471559 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
@@ -73,7 +73,7 @@ int nand_open(void) | |||
73 | /* Init hardware */ | 73 | /* Init hardware */ |
74 | sfc_open(); | 74 | sfc_open(); |
75 | sfc_set_dev_conf(NAND_INIT_SFC_DEV_CONF); | 75 | sfc_set_dev_conf(NAND_INIT_SFC_DEV_CONF); |
76 | sfc_set_clock(NAND_CLOCK_SOURCE, NAND_INIT_CLOCK_SPEED); | 76 | sfc_set_clock(NAND_INIT_CLOCK_SPEED); |
77 | 77 | ||
78 | /* Identify NAND chip */ | 78 | /* Identify NAND chip */ |
79 | int status = 0; | 79 | int status = 0; |
@@ -103,7 +103,7 @@ int nand_open(void) | |||
103 | 103 | ||
104 | /* Configure hardware and run init op */ | 104 | /* Configure hardware and run init op */ |
105 | sfc_set_dev_conf(desc->data->dev_conf); | 105 | sfc_set_dev_conf(desc->data->dev_conf); |
106 | sfc_set_clock(NAND_CLOCK_SOURCE, desc->data->clock_freq); | 106 | sfc_set_clock(desc->data->clock_freq); |
107 | 107 | ||
108 | if((status = desc->ops->open(&nand_driver)) < 0) | 108 | if((status = desc->ops->open(&nand_driver)) < 0) |
109 | goto _err; | 109 | goto _err; |
diff --git a/firmware/target/mips/ingenic_x1000/sfc-x1000.c b/firmware/target/mips/ingenic_x1000/sfc-x1000.c index 4a79be849e..3f1cb25f07 100644 --- a/firmware/target/mips/ingenic_x1000/sfc-x1000.c +++ b/firmware/target/mips/ingenic_x1000/sfc-x1000.c | |||
@@ -33,18 +33,6 @@ | |||
33 | * simple, DMA is unconditionally disabled. */ | 33 | * simple, DMA is unconditionally disabled. */ |
34 | //#define NEED_SFC_DMA | 34 | //#define NEED_SFC_DMA |
35 | 35 | ||
36 | #if defined(BOOTLOADER_SPL) | ||
37 | # if X1000_EXCLK_FREQ == 24000000 | ||
38 | # define FIXED_CLK_FREQ 600000000 | ||
39 | # define FIXED_CLK_SRC X1000_CLK_MPLL | ||
40 | # elif X1000_EXCLK_FREQ == 26000000 | ||
41 | # define FIXED_CLK_FREQ 598000000 | ||
42 | # define FIXED_CLK_SRC X1000_CLK_MPLL | ||
43 | # else | ||
44 | # error "bad EXCLK freq" | ||
45 | # endif | ||
46 | #endif | ||
47 | |||
48 | #define FIFO_THRESH 31 | 36 | #define FIFO_THRESH 31 |
49 | 37 | ||
50 | #define SFC_STATUS_PENDING (-1) | 38 | #define SFC_STATUS_PENDING (-1) |
@@ -111,16 +99,16 @@ void sfc_close(void) | |||
111 | jz_writef(CPM_CLKGR, SFC(1)); | 99 | jz_writef(CPM_CLKGR, SFC(1)); |
112 | } | 100 | } |
113 | 101 | ||
114 | void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq) | 102 | void sfc_set_clock(uint32_t freq) |
115 | { | 103 | { |
116 | uint32_t in_freq; | 104 | /* TODO: This is a hack so we can use MPLL in the SPL. |
117 | #ifdef FIXED_CLK_FREQ | 105 | * There must be a better way to do this... */ |
118 | /* Small optimization to save code space in SPL by not polling clock */ | 106 | x1000_clk_t clksrc = X1000_CLK_MPLL; |
119 | clksrc = FIXED_CLK_SRC; | 107 | uint32_t in_freq = clk_get(clksrc); |
120 | in_freq = FIXED_CLK_FREQ; | 108 | if(in_freq < freq) { |
121 | #else | 109 | clksrc = X1000_CLK_SCLK_A; |
122 | in_freq = clk_get(clksrc); | 110 | in_freq = clk_get(clksrc); |
123 | #endif | 111 | } |
124 | 112 | ||
125 | uint32_t div = clk_calc_div(in_freq, freq); | 113 | uint32_t div = clk_calc_div(in_freq, freq); |
126 | jz_writef(CPM_SSICDR, CE(1), CLKDIV(div - 1), | 114 | jz_writef(CPM_SSICDR, CE(1), CLKDIV(div - 1), |
diff --git a/firmware/target/mips/ingenic_x1000/sfc-x1000.h b/firmware/target/mips/ingenic_x1000/sfc-x1000.h index 283f171697..5784198b93 100644 --- a/firmware/target/mips/ingenic_x1000/sfc-x1000.h +++ b/firmware/target/mips/ingenic_x1000/sfc-x1000.h | |||
@@ -99,7 +99,7 @@ extern void sfc_close(void); | |||
99 | #define sfc_set_wp_enable(en) \ | 99 | #define sfc_set_wp_enable(en) \ |
100 | jz_writef(SFC_GLB, WP_EN((en) ? 1 : 0)) | 100 | jz_writef(SFC_GLB, WP_EN((en) ? 1 : 0)) |
101 | 101 | ||
102 | extern void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq); | 102 | extern void sfc_set_clock(uint32_t freq); |
103 | 103 | ||
104 | /* Execute an operation. Returns zero on success, nonzero on failure. */ | 104 | /* Execute an operation. Returns zero on success, nonzero on failure. */ |
105 | extern int sfc_exec(const sfc_op* op); | 105 | extern int sfc_exec(const sfc_op* op); |