diff options
-rwxr-xr-x | bootloader/mrobe500.c | 5 | ||||
-rw-r--r-- | firmware/export/dm320.h | 2 | ||||
-rw-r--r-- | firmware/target/arm/crt0.S | 2 | ||||
-rwxr-xr-x | firmware/target/arm/tms320dm320/crt0.S | 80 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/system-dm320.c | 20 |
5 files changed, 76 insertions, 33 deletions
diff --git a/bootloader/mrobe500.c b/bootloader/mrobe500.c index a3317f69a4..5817052499 100755 --- a/bootloader/mrobe500.c +++ b/bootloader/mrobe500.c | |||
@@ -42,6 +42,7 @@ | |||
42 | #include "uart-target.h" | 42 | #include "uart-target.h" |
43 | #include "tsc2100.h" | 43 | #include "tsc2100.h" |
44 | #include "time.h" | 44 | #include "time.h" |
45 | #include "system-arm.h" | ||
45 | 46 | ||
46 | #define MRDEBUG | 47 | #define MRDEBUG |
47 | 48 | ||
@@ -168,6 +169,10 @@ void main(void) | |||
168 | lcd_init(); | 169 | lcd_init(); |
169 | system_init(); | 170 | system_init(); |
170 | kernel_init(); | 171 | kernel_init(); |
172 | |||
173 | set_irq_level(0); | ||
174 | set_fiq_status(FIQ_ENABLED); | ||
175 | |||
171 | adc_init(); | 176 | adc_init(); |
172 | button_init(); | 177 | button_init(); |
173 | backlight_init(); | 178 | backlight_init(); |
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index 57ffc8667a..7a64056a4c 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h | |||
@@ -24,7 +24,7 @@ | |||
24 | #ifndef __DM320_H__ | 24 | #ifndef __DM320_H__ |
25 | #define __DM320_H__ | 25 | #define __DM320_H__ |
26 | 26 | ||
27 | #define LCD_BUFFER_SIZE (640*480*4) | 27 | #define LCD_BUFFER_SIZE (640*480*2) |
28 | #define TTB_SIZE (0x4000) | 28 | #define TTB_SIZE (0x4000) |
29 | /* must be 16Kb (0x4000) aligned */ | 29 | /* must be 16Kb (0x4000) aligned */ |
30 | #define TTB_BASE ((unsigned int *)(0x04900000 - TTB_SIZE)) /* End of memory */ | 30 | #define TTB_BASE ((unsigned int *)(0x04900000 - TTB_SIZE)) /* End of memory */ |
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S index 82e4f27ac9..1cc94ba9a2 100644 --- a/firmware/target/arm/crt0.S +++ b/firmware/target/arm/crt0.S | |||
@@ -42,7 +42,7 @@ newstart: | |||
42 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ | 42 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ |
43 | #endif | 43 | #endif |
44 | 44 | ||
45 | #if !defined(BOOTLOADER) || (CONFIG_CPU == DM320) | 45 | #if !defined(BOOTLOADER) |
46 | #if !defined(DEBUG) | 46 | #if !defined(DEBUG) |
47 | /* Copy exception handler code to address 0 */ | 47 | /* Copy exception handler code to address 0 */ |
48 | ldr r2, =_vectorsstart | 48 | ldr r2, =_vectorsstart |
diff --git a/firmware/target/arm/tms320dm320/crt0.S b/firmware/target/arm/tms320dm320/crt0.S index 8c747f7a51..09f936e808 100755 --- a/firmware/target/arm/tms320dm320/crt0.S +++ b/firmware/target/arm/tms320dm320/crt0.S | |||
@@ -28,9 +28,22 @@ | |||
28 | 28 | ||
29 | .global start | 29 | .global start |
30 | start: | 30 | start: |
31 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ | 31 | .equ INTC_IRQ0, 0x00030508 |
32 | .equ INTC_IRQ1, 0x0003050A | ||
33 | .equ INTC_IRQ2, 0x0003050C | ||
34 | .equ INTC_FIQ0, 0x00030500 | ||
35 | .equ INTC_FIQ1, 0x00030502 | ||
36 | .equ INTC_FIQ2, 0x00030504 | ||
37 | .equ INTC_EINT0, 0x00030528 | ||
38 | .equ INTC_EINT1, 0x0003052A | ||
39 | .equ INTC_EINT2, 0x0003052C | ||
40 | .equ INTC_FISEL0, 0x00030520 | ||
41 | .equ INTC_FISEL1, 0x00030522 | ||
42 | .equ INTC_FISEL2, 0x00030524 | ||
43 | .equ INTC_MASK, 0xFFFFFFFF | ||
44 | |||
45 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ | ||
32 | 46 | ||
33 | #if !defined(DEBUG) | ||
34 | /* Copy exception handler code to address 0 */ | 47 | /* Copy exception handler code to address 0 */ |
35 | ldr r2, =_vectorsstart | 48 | ldr r2, =_vectorsstart |
36 | ldr r3, =_vectorsend | 49 | ldr r3, =_vectorsend |
@@ -40,13 +53,6 @@ start: | |||
40 | ldrhi r5, [r4], #4 | 53 | ldrhi r5, [r4], #4 |
41 | strhi r5, [r2], #4 | 54 | strhi r5, [r2], #4 |
42 | bhi 1b | 55 | bhi 1b |
43 | #else | ||
44 | ldr r1, =vectors | ||
45 | ldr r0, =irq_handler | ||
46 | str r0, [r1, #24] | ||
47 | ldr r0, =fiq_handler | ||
48 | str r0, [r1, #28] | ||
49 | #endif | ||
50 | 56 | ||
51 | /* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */ | 57 | /* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */ |
52 | mrc p15, 0, r0, c1, c0, 0 | 58 | mrc p15, 0, r0, c1, c0, 0 |
@@ -58,9 +64,38 @@ start: | |||
58 | orr r0, r0, #0x00000002 | 64 | orr r0, r0, #0x00000002 |
59 | mcr p15, 0, r0, c1, c0, 0 | 65 | mcr p15, 0, r0, c1, c0, 0 |
60 | 66 | ||
61 | #if !defined(BOOTLOADER) | 67 | #if 0 |
68 | /* mask interrupts */ | ||
69 | ldr r1, =INTC_MASK | ||
70 | ldr r2, =INTC_IRQ0 | ||
71 | strh r1, [r2] | ||
72 | ldr r2, =INTC_IRQ1 | ||
73 | strh r1, [r2] | ||
74 | ldr r2, =INTC_IRQ2 | ||
75 | strh r1, [r2] | ||
76 | ldr r2, =INTC_FIQ0 | ||
77 | strh r1, [r2] | ||
78 | ldr r2, =INTC_FIQ1 | ||
79 | strh r1, [r2] | ||
80 | ldr r2, =INTC_FIQ2 | ||
81 | strh r1, [r2] | ||
62 | 82 | ||
63 | #if !defined(STUB) | 83 | mov r1, #0 |
84 | ldr r2, =INTC_EINT0 | ||
85 | strh r1, [r2] | ||
86 | ldr r2, =INTC_EINT1 | ||
87 | strh r1, [r2] | ||
88 | ldr r2, =INTC_EINT2 | ||
89 | strh r1, [r2] | ||
90 | ldr r2, =INTC_FISEL0 | ||
91 | strh r1, [r2] | ||
92 | ldr r2, =INTC_FISEL1 | ||
93 | strh r1, [r2] | ||
94 | ldr r2, =INTC_FISEL2 | ||
95 | strh r1, [r2] | ||
96 | #endif | ||
97 | |||
98 | #if !defined(BOOTLOADER) && !defined(STUB) | ||
64 | /* Zero out IBSS */ | 99 | /* Zero out IBSS */ |
65 | ldr r2, =_iedata | 100 | ldr r2, =_iedata |
66 | ldr r3, =_iend | 101 | ldr r3, =_iend |
@@ -79,8 +114,7 @@ start: | |||
79 | ldrhi r5, [r2], #4 | 114 | ldrhi r5, [r2], #4 |
80 | strhi r5, [r3], #4 | 115 | strhi r5, [r3], #4 |
81 | bhi 1b | 116 | bhi 1b |
82 | #endif /* !STUB */ | 117 | #endif /* !BOOTLOADER,!STUB */ |
83 | #endif /* !BOOTLOADER */ | ||
84 | 118 | ||
85 | /* Initialise bss section to zero */ | 119 | /* Initialise bss section to zero */ |
86 | ldr r2, =_edata | 120 | ldr r2, =_edata |
@@ -90,28 +124,31 @@ start: | |||
90 | cmp r3, r2 | 124 | cmp r3, r2 |
91 | strhi r4, [r2], #4 | 125 | strhi r4, [r2], #4 |
92 | bhi 1b | 126 | bhi 1b |
93 | 127 | ||
128 | /* Load stack munge value */ | ||
129 | ldr r4, =0xdeadbeef | ||
130 | |||
94 | /* Set up some stack and munge it with 0xdeadbeef */ | 131 | /* Set up some stack and munge it with 0xdeadbeef */ |
95 | ldr r3, =stackend | ||
96 | ldr r2, =stackbegin | 132 | ldr r2, =stackbegin |
97 | ldr r4, =0xdeadbeef | 133 | ldr r3, =stackend |
98 | 1: | 134 | 1: |
99 | cmp r3, r2 | 135 | cmp r3, r2 |
100 | strhi r4, [r2], #4 | 136 | strhi r4, [r2], #4 |
101 | bhi 1b | 137 | bhi 1b |
102 | 138 | ||
103 | /* Set up stack for IRQ mode */ | 139 | /* Set up stack for IRQ mode */ |
104 | msr cpsr_c, #0xd2 | 140 | msr cpsr_c, #0x92 /* IRQ disabled, FIQ enabled */ |
105 | ldr sp, =irq_stack | 141 | ldr sp, =irq_stack |
106 | /* Set up stack for FIQ mode */ | 142 | /* Set up stack for FIQ mode */ |
107 | msr cpsr_c, #0xd1 | 143 | msr cpsr_c, #0xd1 /* IRQ/FIQ disabled */ |
108 | ldr sp, =fiq_stack | 144 | ldr sp, =fiq_stack |
109 | 145 | ||
110 | /* Let abort and undefined modes use IRQ stack */ | 146 | /* Let abort and undefined modes use IRQ stack */ |
111 | msr cpsr_c, #0xd7 | 147 | msr cpsr_c, #0xd7 /* IRQ/FIQ disabled */ |
112 | ldr sp, =irq_stack | 148 | ldr sp, =irq_stack |
113 | msr cpsr_c, #0xdb | 149 | msr cpsr_c, #0xdb /* IRQ/FIQ disabled */ |
114 | ldr sp, =irq_stack | 150 | ldr sp, =irq_stack |
151 | |||
115 | /* Switch to supervisor mode (no IRQ) */ | 152 | /* Switch to supervisor mode (no IRQ) */ |
116 | msr cpsr_c, #0xd3 | 153 | msr cpsr_c, #0xd3 |
117 | ldr sp, =stackend | 154 | ldr sp, =stackend |
@@ -203,6 +240,9 @@ UIE: | |||
203 | b UIE | 240 | b UIE |
204 | #endif | 241 | #endif |
205 | 242 | ||
243 | /* Align stacks to cache line boundary */ | ||
244 | .balign 16 | ||
245 | |||
206 | /* 256 words of IRQ stack */ | 246 | /* 256 words of IRQ stack */ |
207 | .space 256*4 | 247 | .space 256*4 |
208 | irq_stack: | 248 | irq_stack: |
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c index f3f8dcea26..c009766f21 100644 --- a/firmware/target/arm/tms320dm320/system-dm320.c +++ b/firmware/target/arm/tms320dm320/system-dm320.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include "system.h" | 22 | #include "system.h" |
23 | #include "panic.h" | 23 | #include "panic.h" |
24 | #include "uart-target.h" | 24 | #include "uart-target.h" |
25 | #include "system-arm.h" | ||
25 | #include "spi.h" | 26 | #include "spi.h" |
26 | 27 | ||
27 | #define default_interrupt(name) \ | 28 | #define default_interrupt(name) \ |
@@ -143,11 +144,6 @@ void system_reboot(void) | |||
143 | 144 | ||
144 | } | 145 | } |
145 | 146 | ||
146 | void enable_interrupts (void) | ||
147 | { | ||
148 | asm volatile ("msr cpsr_c, #0x13" ); | ||
149 | } | ||
150 | |||
151 | void system_init(void) | 147 | void system_init(void) |
152 | { | 148 | { |
153 | /* taken from linux/arch/arm/mach-itdm320-20/irq.c */ | 149 | /* taken from linux/arch/arm/mach-itdm320-20/irq.c */ |
@@ -171,22 +167,24 @@ void system_init(void) | |||
171 | IO_INTC_FISEL1 = 0; | 167 | IO_INTC_FISEL1 = 0; |
172 | IO_INTC_FISEL2 = 0; | 168 | IO_INTC_FISEL2 = 0; |
173 | 169 | ||
174 | IO_INTC_ENTRY_TBA0 = | 170 | IO_INTC_ENTRY_TBA0 = 0; |
175 | IO_INTC_ENTRY_TBA1 = 0; | 171 | IO_INTC_ENTRY_TBA1 = 0; |
176 | 172 | ||
177 | /* set GIO26 (reset pin) to output and low */ | 173 | /* set GIO26 (reset pin) to output and low */ |
178 | IO_GIO_BITCLR1=(1<<10); | 174 | IO_GIO_BITCLR1=(1<<10); |
179 | IO_GIO_DIR1&=~(1<<10); | 175 | IO_GIO_DIR1&=~(1<<10); |
180 | 176 | ||
181 | enable_interrupts(); | ||
182 | uart_init(); | 177 | uart_init(); |
183 | spi_init(); | 178 | spi_init(); |
184 | 179 | ||
185 | /* MMU initialization (Starts data and instruction cache) */ | 180 | /* MMU initialization (Starts data and instruction cache) */ |
186 | ttb_init(); | 181 | ttb_init(); |
187 | map_section(0, 0, 0x1000, CACHE_NONE); /* Make sure everything is mapped on itself */ | 182 | /* Make sure everything is mapped on itself */ |
188 | map_section(0x00900000, 0x00900000, 64, CACHE_ALL); /* Enable caching for RAM */ | 183 | map_section(0, 0, 0x1000, CACHE_NONE); |
189 | map_section((int)FRAME, (int)FRAME, 2, BUFFERED); /* enable buffered writing for the framebuffer */ | 184 | /* Enable caching for RAM */ |
185 | map_section(0x00900000, 0x00900000, 64, CACHE_ALL); | ||
186 | /* enable buffered writing for the framebuffer */ | ||
187 | map_section((int)FRAME, (int)FRAME, 1, BUFFERED); | ||
190 | enable_mmu(); | 188 | enable_mmu(); |
191 | } | 189 | } |
192 | 190 | ||