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author | Amaury Pouly <amaury.pouly@gmail.com> | 2016-08-02 15:18:41 +0100 |
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committer | Amaury Pouly <amaury.pouly@gmail.com> | 2017-01-24 15:25:14 +0100 |
commit | 56340f4cd0a6ab318a52d2a62ded36aad2946e1d (patch) | |
tree | 32cb9a8380131b93249abd4ab68d2ebaf7dcc541 /utils/hwstub/stub/jz4760b | |
parent | 83155f32bfa3e8f3641b81098744431f6fc59e56 (diff) | |
download | rockbox-56340f4cd0a6ab318a52d2a62ded36aad2946e1d.tar.gz rockbox-56340f4cd0a6ab318a52d2a62ded36aad2946e1d.zip |
hwstub: add the possibility to flush caches before exec
This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h
Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e
Diffstat (limited to 'utils/hwstub/stub/jz4760b')
-rw-r--r-- | utils/hwstub/stub/jz4760b/target-config.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/utils/hwstub/stub/jz4760b/target-config.h b/utils/hwstub/stub/jz4760b/target-config.h index fa018c14dc..681e17e6f6 100644 --- a/utils/hwstub/stub/jz4760b/target-config.h +++ b/utils/hwstub/stub/jz4760b/target-config.h | |||
@@ -3,6 +3,12 @@ | |||
3 | #define TCSM0_SIZE 0x4000 | 3 | #define TCSM0_SIZE 0x4000 |
4 | #define CPU_MIPS | 4 | #define CPU_MIPS |
5 | #define STACK_SIZE 0x300 | 5 | #define STACK_SIZE 0x300 |
6 | #define DCACHE_SIZE 0x4000 /* 16 kB */ | ||
7 | #define DCACHE_LINE_SIZE 0x20 /* 32 B */ | ||
8 | #define ICACHE_SIZE 0x4000 /* 16 kB */ | ||
9 | #define ICACHE_LINE_SIZE 0x20 /* 32 B */ | ||
10 | /* we need to flush caches before executing */ | ||
11 | #define CONFIG_FLUSH_CACHES | ||
6 | 12 | ||
7 | /* something provides define | 13 | /* something provides define |
8 | * #define mips 1 | 14 | * #define mips 1 |