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author | Amaury Pouly <amaury.pouly@gmail.com> | 2016-08-02 15:18:41 +0100 |
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committer | Amaury Pouly <amaury.pouly@gmail.com> | 2017-01-24 15:25:14 +0100 |
commit | 56340f4cd0a6ab318a52d2a62ded36aad2946e1d (patch) | |
tree | 32cb9a8380131b93249abd4ab68d2ebaf7dcc541 /utils/hwstub/stub/asm | |
parent | 83155f32bfa3e8f3641b81098744431f6fc59e56 (diff) | |
download | rockbox-56340f4cd0a6ab318a52d2a62ded36aad2946e1d.tar.gz rockbox-56340f4cd0a6ab318a52d2a62ded36aad2946e1d.zip |
hwstub: add the possibility to flush caches before exec
This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h
Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e
Diffstat (limited to 'utils/hwstub/stub/asm')
-rw-r--r-- | utils/hwstub/stub/asm/mips/system.S | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/utils/hwstub/stub/asm/mips/system.S b/utils/hwstub/stub/asm/mips/system.S index ab134aed48..97b0207ec9 100644 --- a/utils/hwstub/stub/asm/mips/system.S +++ b/utils/hwstub/stub/asm/mips/system.S | |||
@@ -18,6 +18,7 @@ | |||
18 | * | 18 | * |
19 | ****************************************************************************/ | 19 | ****************************************************************************/ |
20 | #include "mips.h" | 20 | #include "mips.h" |
21 | #include "target-config.h" | ||
21 | 22 | ||
22 | /* Handling of data abort: | 23 | /* Handling of data abort: |
23 | * the code can register a "longjmp" buffer to restore the context in case of | 24 | * the code can register a "longjmp" buffer to restore the context in case of |
@@ -49,3 +50,27 @@ set_data_abort_jmp: | |||
49 | jr ra | 50 | jr ra |
50 | move v0, zero | 51 | move v0, zero |
51 | .set reorder | 52 | .set reorder |
53 | |||
54 | #ifdef CONFIG_FLUSH_CACHES | ||
55 | .set noreorder | ||
56 | .text | ||
57 | .global target_flush_caches | ||
58 | target_flush_caches: | ||
59 | /* commit dcache and invalidate icache */ | ||
60 | la t0, 0x80000000 /* an idx op should use an unmappable address */ | ||
61 | ori t1, t0, DCACHE_SIZE /* cache size */ | ||
62 | reloc_dcache_loop: | ||
63 | cache DCIndexWBInv, 0(t0) /* invalidate and write-back dcache index */ | ||
64 | addiu t0, t0, DCACHE_LINE_SIZE /* bytes per cache line */ | ||
65 | bne t0, t1, reloc_dcache_loop | ||
66 | nop | ||
67 | la t0, 0x80000000 /* an idx op should use an unmappable address */ | ||
68 | ori t1, t0, ICACHE_SIZE /* cache size */ | ||
69 | reloc_icache_loop: | ||
70 | cache ICIndexInv, 0(t0) /* invalidate icache index */ | ||
71 | addiu t0, t0, ICACHE_LINE_SIZE /* bytes per cache line */ | ||
72 | bne t0, t1, reloc_icache_loop | ||
73 | nop | ||
74 | jr ra | ||
75 | nop | ||
76 | #endif | ||