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authorRafaël Carré <rafael.carre@gmail.com>2010-02-21 22:01:23 +0000
committerRafaël Carré <rafael.carre@gmail.com>2010-02-21 22:01:23 +0000
commitad7d84d3150ce9ad047e5637ba004c93f7ab88cb (patch)
tree3c01fc7ded03dfd6770c3310a25e0a7c62c5d0cc /firmware
parentd19705f7fc9f0c7b245a40a11a5dc9174ae83c3f (diff)
downloadrockbox-ad7d84d3150ce9ad047e5637ba004c93f7ab88cb.tar.gz
rockbox-ad7d84d3150ce9ad047e5637ba004c93f7ab88cb.zip
sd-as3525v2: command register bits
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24829 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/target/arm/as3525/sd-as3525v2.c139
1 files changed, 47 insertions, 92 deletions
diff --git a/firmware/target/arm/as3525/sd-as3525v2.c b/firmware/target/arm/as3525/sd-as3525v2.c
index 862cf3ca13..72a3631bb7 100644
--- a/firmware/target/arm/as3525/sd-as3525v2.c
+++ b/firmware/target/arm/as3525/sd-as3525v2.c
@@ -43,6 +43,7 @@
43#include <stdarg.h> 43#include <stdarg.h>
44#include "sysfont.h" 44#include "sysfont.h"
45 45
46/* debug helper */
46static int line = 0; 47static int line = 0;
47static void printf(const char *format, ...) 48static void printf(const char *format, ...)
48{ 49{
@@ -61,85 +62,18 @@ static void printf(const char *format, ...)
61} 62}
62 63
63/* command flags */ 64/* command flags */
64#define MCI_NO_RESP (0<<0) 65#define MCI_NO_RESP (0<<0)
65#define MCI_RESP (1<<0) 66#define MCI_RESP (1<<0)
66#define MCI_LONG_RESP (1<<1) 67#define MCI_LONG_RESP (1<<1)
67 68
68/* controller registers */ 69/* controller registers */
69#define SD_BASE 0xC6070000 70#define SD_BASE 0xC6070000
70 71
71/*
72 * STATUS register
73 * & 0xBA80 = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
74 * MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
75 * & 8 = MCI_INT_DTO
76 * & 0x428 = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
77 * & 0x418 = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
78 */
79
80/*
81 * INFO on CMD register
82 *
83 * if(cmd >= 200) cmd -= 200; (>= 200 = acmd?)
84 *
85 * COMMANDS (| (x<<16) BITS RESPONSE
86 *
87 * 1 ? reserved & ~0x80, | 0x40, | 0x8000 ?
88 * 5 ? reserved for I/O cards & ~0x80, | 0x40 ?
89 * 11 ? reserved & ~0x80, | 0x40, | 0x2200, | 0x800 ?
90 * 14 ? reserved & ~0x80, | 0x40, | 0x2200, ~0x1000 ?
91 * 19 ? reserved & ~0x80, |0x40, | 0x2700, & ~0x1000 ?
92 * 20 ? reserved & ~0x80, |0x40, | 0x2700, | 0x800 ?
93 * 23 ? reserved & ~0x80, | 0x40 ?
94 * 39 ? reserved & ~0x80, | 0x40 ?
95 * 51 ? reserved & ~0x80, | 0x40, | 0x2000, | 0x200 ?
96 * 52 ? reserved for I/O & ~0x80, | 0x40 ?
97 * 53 ? reserved for I/O & ~0x80, | 0x40, | 0x2200, & ~0x1000 ?
98 * 253 ? & ~0x80, |0x40, | 0x2700, & ~0x1000 ?
99 *
100 * 0 GO IDLE STATE & ~0x4000, & ~0xC0, | 0x4000 no
101 * 2 ALL SEND CID & ~0x4000, |0xC0 r2
102 * 3 SEND RCA & ~0x80, | 0x40 r6
103 * 6 SWITCH_FUNC & ~0x80, | 0x40 r1
104 * 7 SELECT CARD & ~0x80, | 0x40 r1b
105 * 8 SEND IF COND & ~0x80, | 0x40, | 0x2200, & ~0x1000 r7
106 * 9 SEND CSD & ~0x4000, | 0xc0 r2
107 * 12 STOP TRANSMISSION & ~0x80, | 0x40, | 0x4000 r1b
108 * 13 SEND STATUS & ~0x80, | 0x40 r1
109 * 15 GO INACTIVE STATE & ~0x4000, & ~0xC0 no
110 * 16 SET BLOCKLEN & ~0x80, | 0x40 r1
111 * 17 READ SINGLE BLOCK & ~0x80, | 0x40, | 0x2200 r1
112 * 18 READ MULTIPLE BLOCK & ~0x80, | 0x40, | 0x2200 r1
113 * 24 WRITE BLOCK & ~0x80, |0x40, | 0x2700 r1
114 * 25 WRITE MULTIPLE BLOCK & ~0x80, |0x40, | 0x2700 r1
115 * 41 SEND APP OP COND & ~0x80, | 0x40 r3
116 * 42 LOCK UNLOCK & ~0x80, |0x40, | 0x2700 r1
117 * 55 APP CMD & ~0x80, | 0x40 r1
118 * 206 SET BUS WIDTH & ~0x80, | 0x40, | 0x2000 r1
119 * 207 SELECT CARD ? & ~0x4000, & ~0xC0 r1b
120 *
121 *
122 * bits 5:0 = cmd
123 * bit 6 (0x40) = response
124 * bit 7 (0x80) = long response
125 * => like pl180 <=
126 * BIT SET IN COMANDS:
127 *
128 * bit 8 (0x100) ? write block, write multi_block, lock/unlock
129 * bit 9 (0x200) ? send if cond, read block, read multi_block, write block, write multi_block, lock/unlock
130 * bit 10 (0x400) ? write block, write multi_block, lock/unlock
131 * bit 11 (0x800) ?
132 * bit 12 (0x1000) ?
133 * bit 13 (0x2000) ? send if cond, read block, read multi_block, write block, write multi_block, lock/unlock, set bus width
134 * bit 14 (0x4000) ? go idle state, stop transmission
135 * bit 15 (0x8000) ?
136 *
137 */
138
139#define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x)) 72#define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x))
140 73
141#define MCI_CTRL SD_REG(0x00) 74#define MCI_CTRL SD_REG(0x00)
142 75
76/* control bits */
143#define CTRL_RESET (1<<0) 77#define CTRL_RESET (1<<0)
144#define FIFO_RESET (1<<1) 78#define FIFO_RESET (1<<1)
145#define DMA_RESET (1<<2) 79#define DMA_RESET (1<<2)
@@ -169,6 +103,23 @@ static void printf(const char *format, ...)
169#define MCI_ARGUMENT SD_REG(0x28) 103#define MCI_ARGUMENT SD_REG(0x28)
170#define MCI_COMMAND SD_REG(0x2C) 104#define MCI_COMMAND SD_REG(0x2C)
171 105
106/* command bits (bits 5:0 are the command index) */
107#define CMD_RESP_EXP_BIT (1<<6)
108#define CMD_RESP_LENGTH_BIT (1<<7)
109#define CMD_CHECK_CRC_BIT (1<<8)
110#define CMD_DATA_EXP_BIT (1<<9)
111#define CMD_RW_BIT (1<<10)
112#define CMD_TRANSMODE_BIT (1<<11)
113#define CMD_SENT_AUTO_STOP_BIT (1<<12)
114#define CMD_WAIT_PRV_DAT_BIT (1<<13)
115#define CMD_ABRT_CMD_BIT (1<<14)
116#define CMD_SEND_INIT_BIT (1<<15)
117#define CMD_SEND_CLK_ONLY (1<<21)
118#define CMD_READ_CEATA (1<<22)
119#define CMD_CCS_EXPECTED (1<<23)
120#define CMD_DONE_BIT (1<<31)
121
122
172#define MCI_RESP0 SD_REG(0x30) 123#define MCI_RESP0 SD_REG(0x30)
173#define MCI_RESP1 SD_REG(0x34) 124#define MCI_RESP1 SD_REG(0x34)
174#define MCI_RESP2 SD_REG(0x38) 125#define MCI_RESP2 SD_REG(0x38)
@@ -179,6 +130,15 @@ static void printf(const char *format, ...)
179 * status clear */ 130 * status clear */
180#define MCI_STATUS SD_REG(0x48) 131#define MCI_STATUS SD_REG(0x48)
181 132
133/*
134 * STATUS register
135 * & 0xBA80 = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
136 * MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
137 * & 8 = MCI_INT_DTO
138 * & 0x428 = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
139 * & 0x418 = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
140 */
141
182/* interrupt bits */ 142/* interrupt bits */
183#define MCI_INT_CRDDET (1<<0) 143#define MCI_INT_CRDDET (1<<0)
184#define MCI_INT_RE (1<<1) 144#define MCI_INT_RE (1<<1)
@@ -222,13 +182,6 @@ static void printf(const char *format, ...)
222 182
223#define MCI_FIFO ((unsigned long *) (SD_BASE+0x100)) 183#define MCI_FIFO ((unsigned long *) (SD_BASE+0x100))
224 184
225#define MCI_COMMAND_ENABLE (1<<31)
226#define MCI_COMMAND_ACTIVE MCI_COMMAND_ENABLE
227#define MCI_COMMAND_RESPONSE (1<<6)
228#define MCI_COMMAND_LONG_RESPONSE (1<<7)
229
230
231
232static int sd_init_card(void); 185static int sd_init_card(void);
233static void init_controller(void); 186static void init_controller(void);
234 187
@@ -318,41 +271,43 @@ static bool send_cmd(const int cmd, const int arg, const int flags,
318 unsigned long *response) 271 unsigned long *response)
319{ 272{
320 int val; 273 int val;
321 val = cmd | MCI_COMMAND_ENABLE; 274 val = cmd | CMD_DONE_BIT;
322 if(flags & MCI_RESP) 275 if(flags & MCI_RESP)
323 { 276 {
324 val |= MCI_COMMAND_RESPONSE; 277 val |= CMD_RESP_EXP_BIT;
325 if(flags & MCI_LONG_RESP) 278 if(flags & MCI_LONG_RESP)
326 val |= MCI_COMMAND_LONG_RESPONSE; 279 val |= CMD_RESP_LENGTH_BIT;
327 } 280 }
328 281
329 if(cmd == 18) /* r */ 282 if(cmd == SD_READ_MULTIPLE_BLOCK || cmd == SD_WRITE_MULTIPLE_BLOCK)
330 val |= 0x2200; 283 {
331 else if(cmd == 25) /* w */ 284 val |= CMD_WAIT_PRV_DAT_BIT | CMD_DATA_EXP_BIT;
332 val |= 0x2700; 285 if(cmd == SD_WRITE_MULTIPLE_BLOCK)
286 val |= CMD_RW_BIT | CMD_CHECK_CRC_BIT;
287 }
333 288
334 int tmp = MCI_CLKENA; 289 int tmp = MCI_CLKENA;
335 MCI_CLKENA = 0; 290 MCI_CLKENA = 0;
336 291
337 MCI_COMMAND = 0x80202000; 292 MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
338 MCI_ARGUMENT = 0; 293 MCI_ARGUMENT = 0;
339 int max = 10; 294 int max = 10;
340 while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); 295 while(max-- && MCI_COMMAND & CMD_DONE_BIT);
341 296
342 MCI_CLKDIV &= ~0xff; 297 MCI_CLKDIV &= ~0xff;
343 MCI_CLKDIV |= 0; 298 MCI_CLKDIV |= 0;
344 299
345 MCI_COMMAND = 0x80202000; 300 MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
346 MCI_ARGUMENT = 0; 301 MCI_ARGUMENT = 0;
347 max = 10; 302 max = 10;
348 while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); 303 while(max-- && MCI_COMMAND & CMD_DONE_BIT);
349 304
350 MCI_CLKENA = tmp; 305 MCI_CLKENA = tmp;
351 306
352 MCI_COMMAND = 0x80202000; 307 MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
353 MCI_ARGUMENT = 0; 308 MCI_ARGUMENT = 0;
354 max = 10; 309 max = 10;
355 while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); 310 while(max-- && MCI_COMMAND & CMD_DONE_BIT);
356 311
357 mci_delay(); 312 mci_delay();
358 313
@@ -362,7 +317,7 @@ static bool send_cmd(const int cmd, const int arg, const int flags,
362 MCI_CTRL |= INT_ENABLE; 317 MCI_CTRL |= INT_ENABLE;
363 318
364 max = 1000; 319 max = 1000;
365 while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); /* wait for cmd completion */ 320 while(max-- && MCI_COMMAND & CMD_DONE_BIT); /* wait for cmd completion */
366 if(!max) 321 if(!max)
367 return false; 322 return false;
368 323
@@ -538,9 +493,9 @@ static void init_controller(void)
538 MCI_CLKENA = (1<<shift) - 1; 493 MCI_CLKENA = (1<<shift) - 1;
539 494
540 MCI_ARGUMENT = 0; 495 MCI_ARGUMENT = 0;
541 MCI_COMMAND = 0x80202000; 496 MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
542 int max = 10; 497 int max = 10;
543 while(max-- && (MCI_COMMAND & (1<<31))) ; 498 while(max-- && (MCI_COMMAND & CMD_DONE_BIT)) ;
544 499
545 MCI_DEBNCE = 0xfffff; /* default value */ 500 MCI_DEBNCE = 0xfffff; /* default value */
546 501