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author | Rafaël Carré <rafael.carre@gmail.com> | 2010-02-21 22:01:05 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-02-21 22:01:05 +0000 |
commit | 48ed5ad66e15bfb30bb42ca5cc62cd67732976f5 (patch) | |
tree | c6f356fef3a223b4f0fe7689c3eeca4d0040e48c /firmware | |
parent | 34ae3959e6724f339c975a64b37e9141a3ea08df (diff) | |
download | rockbox-48ed5ad66e15bfb30bb42ca5cc62cd67732976f5.tar.gz rockbox-48ed5ad66e15bfb30bb42ca5cc62cd67732976f5.zip |
as3525v2: full list of registers + description
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24825 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/as3525/sd-as3525v2.c | 157 |
1 files changed, 77 insertions, 80 deletions
diff --git a/firmware/target/arm/as3525/sd-as3525v2.c b/firmware/target/arm/as3525/sd-as3525v2.c index ccd5a7890f..8484429e9f 100644 --- a/firmware/target/arm/as3525/sd-as3525v2.c +++ b/firmware/target/arm/as3525/sd-as3525v2.c | |||
@@ -69,36 +69,6 @@ static void printf(const char *format, ...) | |||
69 | #define SD_BASE 0xC6070000 | 69 | #define SD_BASE 0xC6070000 |
70 | 70 | ||
71 | /* | 71 | /* |
72 | * REGISTERS | ||
73 | * | ||
74 | * m = modify (orr/bic), r = read, w = write | ||
75 | * | ||
76 | * 00 m/r/w | ||
77 | * 04 m/w | ||
78 | * 08 m | ||
79 | * 0C ? | ||
80 | * 10 r/w | ||
81 | * 14 w | ||
82 | * 18 m | ||
83 | * 1C w ==> set a bit before transfer (sometimes) ! | ||
84 | * 20 w ==> set a bit before transfer ! | ||
85 | * 24 w irq mask ? | ||
86 | * 28 w arg | ||
87 | * 2C r/w cmd | ||
88 | * 30 r resp0 | ||
89 | * 34 r resp1 | ||
90 | * 38 r resp2 | ||
91 | * 3C r resp3 | ||
92 | * 40 r irq status (only read in isr) | ||
93 | * 44 m/w irq clear | ||
94 | * 48 r | ||
95 | * 4C m | ||
96 | * 64 w | ||
97 | * 70 r | ||
98 | * 100 FIFO | ||
99 | */ | ||
100 | |||
101 | /* | ||
102 | * STATUS register | 72 | * STATUS register |
103 | * & 0xBA80 | 73 | * & 0xBA80 |
104 | * & 8 | 74 | * & 8 |
@@ -165,23 +135,50 @@ static void printf(const char *format, ...) | |||
165 | * | 135 | * |
166 | */ | 136 | */ |
167 | 137 | ||
168 | /* FIXME */ | 138 | #define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x)) |
169 | #define MCI_POWER | 139 | |
170 | #define MCI_CLOCK | 140 | #define MCI_CTRL SD_REG(0x00) |
171 | #define MCI_ARGUMENT (*(volatile unsigned long *) (SD_BASE+0x28)) | 141 | #define MCI_PWREN SD_REG(0x04) /* power enable */ |
172 | #define MCI_COMMAND (*(volatile unsigned long *) (SD_BASE+0x2C)) | 142 | #define MCI_CLKDIV SD_REG(0x08) /* clock divider */ |
173 | #define MCI_RESPCMD | 143 | #define MCI_CLKSRC SD_REG(0x0C) /* clock source */ |
174 | #define MCI_RESP0 (*(volatile unsigned long *) (SD_BASE+0x30)) | 144 | #define MCI_CLKENA SD_REG(0x10) /* clock enable */ |
175 | #define MCI_RESP1 (*(volatile unsigned long *) (SD_BASE+0x34)) | 145 | #define MCI_TMOUT SD_REG(0x14) /* timeout */ |
176 | #define MCI_RESP2 (*(volatile unsigned long *) (SD_BASE+0x38)) | 146 | #define MCI_CTYPE SD_REG(0x18) /* card type */ |
177 | #define MCI_RESP3 (*(volatile unsigned long *) (SD_BASE+0x3C)) | 147 | #define MCI_BLKSIZ SD_REG(0x1C) /* block size */ |
178 | #define MCI_DATA_TIMER | 148 | #define MCI_BYTCNT SD_REG(0x20) /* byte count */ |
179 | #define MCI_DATA_LENGTH | 149 | #define MCI_MASK SD_REG(0x24) /* interrupt mask */ |
180 | #define MCI_DATA_CTRL | 150 | |
181 | #define MCI_STATUS (*(volatile unsigned long *) (SD_BASE+0x40)) | 151 | #define MCI_ARGUMENT SD_REG(0x28) |
182 | #define MCI_CLEAR (*(volatile unsigned long *) (SD_BASE+0x44)) | 152 | #define MCI_COMMAND SD_REG(0x2C) |
183 | #define MCI_MASK (*(volatile unsigned long *) (SD_BASE+0x24)) | 153 | |
184 | #define MCI_SELECT | 154 | #define MCI_RESP0 SD_REG(0x30) |
155 | #define MCI_RESP1 SD_REG(0x34) | ||
156 | #define MCI_RESP2 SD_REG(0x38) | ||
157 | #define MCI_RESP3 SD_REG(0x3C) | ||
158 | |||
159 | #define MCI_MASK_STATUS SD_REG(0x40) /* masked interrupt status */ | ||
160 | #define MCI_RAW_STATUS SD_REG(0x44) /* raw interrupt status, also used as | ||
161 | * status clear */ | ||
162 | #define MCI_STATUS SD_REG(0x48) | ||
163 | |||
164 | #define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */ | ||
165 | #define MCI_CDETECT SD_REG(0x50) /* card detect */ | ||
166 | #define MCI_WRTPRT SD_REG(0x54) /* write protect */ | ||
167 | #define MCI_GPIO SD_REG(0x58) | ||
168 | #define MCI_TCBCNT SD_REG(0x5C) /* transferred CIU byte count */ | ||
169 | #define MCI_TBBCNT SD_REG(0x60) /* transferred host/DMA to/from bytes */ | ||
170 | #define MCI_DEBNCE SD_REG(0x64) /* card detect debounce */ | ||
171 | #define MCI_USRID SD_REG(0x68) /* user id */ | ||
172 | #define MCI_VERID SD_REG(0x6C) /* version id */ | ||
173 | #define MCI_HCON SD_REG(0x70) /* hardware config */ | ||
174 | |||
175 | #define MCI_BMOD SD_REG(0x80) /* bus mode */ | ||
176 | #define MCI_PLDMND SD_REG(0x84) /* poll demand */ | ||
177 | #define MCI_DBADDR SD_REG(0x88) /* descriptor base address */ | ||
178 | #define MCI_IDSTS SD_REG(0x8C) /* internal DMAC status */ | ||
179 | #define MCI_IDINTEN SD_REG(0x90) /* internal DMAC interrupt enable */ | ||
180 | #define MCI_DSCADDR SD_REG(0x94) /* current host descriptor address */ | ||
181 | #define MCI_BUFADDR SD_REG(0x98) /* current host buffer address */ | ||
185 | 182 | ||
186 | #define MCI_ERROR 0 /* FIXME */ | 183 | #define MCI_ERROR 0 /* FIXME */ |
187 | 184 | ||
@@ -220,7 +217,7 @@ static inline void mci_delay(void) { int i = 0xffff; while(i--) ; } | |||
220 | 217 | ||
221 | void INT_NAND(void) | 218 | void INT_NAND(void) |
222 | { | 219 | { |
223 | (*(volatile unsigned long *) (SD_BASE+0x0)) &= ~0x10; // ? | 220 | MCI_CTRL &= ~0x10; // ? |
224 | const int status = MCI_STATUS; | 221 | const int status = MCI_STATUS; |
225 | 222 | ||
226 | #if 0 | 223 | #if 0 |
@@ -229,7 +226,7 @@ void INT_NAND(void) | |||
229 | #endif | 226 | #endif |
230 | 227 | ||
231 | // wakeup_signal(&transfer_completion_signal); | 228 | // wakeup_signal(&transfer_completion_signal); |
232 | MCI_CLEAR = status; | 229 | MCI_RAW_STATUS = status; |
233 | 230 | ||
234 | //static int x = 0; | 231 | //static int x = 0; |
235 | switch(status) | 232 | switch(status) |
@@ -264,11 +261,11 @@ void INT_NAND(void) | |||
264 | * read resp (6, 7, 12, 42) : while bit 9 is unset ; | 261 | * read resp (6, 7, 12, 42) : while bit 9 is unset ; |
265 | * | 262 | * |
266 | */ | 263 | */ |
267 | //printf("%x %x", status, (*(volatile unsigned long *) (SD_BASE+0x48))); | 264 | //printf("%x %x", status, MCI_STATUS); |
268 | //while(!button_read_device()); | 265 | //while(!button_read_device()); |
269 | //while(button_read_device()); | 266 | //while(button_read_device()); |
270 | 267 | ||
271 | (*(volatile unsigned long *) (SD_BASE+0x0)) |= 0x10; // ? | 268 | MCI_CTRL |= 0x10; // ? |
272 | } | 269 | } |
273 | 270 | ||
274 | static bool send_cmd(const int cmd, const int arg, const int flags, | 271 | static bool send_cmd(const int cmd, const int arg, const int flags, |
@@ -288,23 +285,23 @@ static bool send_cmd(const int cmd, const int arg, const int flags, | |||
288 | else if(cmd == 25) /* w */ | 285 | else if(cmd == 25) /* w */ |
289 | val |= 0x2700; | 286 | val |= 0x2700; |
290 | 287 | ||
291 | int tmp = (*(volatile unsigned long *) (SD_BASE+0x10)); | 288 | int tmp = MCI_CLKENA; |
292 | (*(volatile unsigned long *) (SD_BASE+0x10)) = 0; | 289 | MCI_CLKENA = 0; |
293 | 290 | ||
294 | MCI_COMMAND = 0x80202000; | 291 | MCI_COMMAND = 0x80202000; |
295 | MCI_ARGUMENT = 0; | 292 | MCI_ARGUMENT = 0; |
296 | int max = 10; | 293 | int max = 10; |
297 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); | 294 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); |
298 | 295 | ||
299 | (*(volatile unsigned long *) (SD_BASE+0x08)) &= ~0xff; | 296 | MCI_CLKDIV &= ~0xff; |
300 | (*(volatile unsigned long *) (SD_BASE+0x08)) |= 0; | 297 | MCI_CLKDIV |= 0; |
301 | 298 | ||
302 | MCI_COMMAND = 0x80202000; | 299 | MCI_COMMAND = 0x80202000; |
303 | MCI_ARGUMENT = 0; | 300 | MCI_ARGUMENT = 0; |
304 | max = 10; | 301 | max = 10; |
305 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); | 302 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); |
306 | 303 | ||
307 | (*(volatile unsigned long *) (SD_BASE+0x10)) = tmp; | 304 | MCI_CLKENA = tmp; |
308 | 305 | ||
309 | MCI_COMMAND = 0x80202000; | 306 | MCI_COMMAND = 0x80202000; |
310 | MCI_ARGUMENT = 0; | 307 | MCI_ARGUMENT = 0; |
@@ -316,7 +313,7 @@ static bool send_cmd(const int cmd, const int arg, const int flags, | |||
316 | MCI_ARGUMENT = arg; | 313 | MCI_ARGUMENT = arg; |
317 | MCI_COMMAND = val; | 314 | MCI_COMMAND = val; |
318 | 315 | ||
319 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x10; | 316 | MCI_CTRL |= 0x10; |
320 | 317 | ||
321 | max = 1000; | 318 | max = 1000; |
322 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); /* wait for cmd completion */ | 319 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); /* wait for cmd completion */ |
@@ -412,8 +409,8 @@ static int sd_init_card(void) | |||
412 | if(!send_cmd(SD_SET_BUS_WIDTH, card_info.rca | 2, MCI_NO_RESP, NULL)) | 409 | if(!send_cmd(SD_SET_BUS_WIDTH, card_info.rca | 2, MCI_NO_RESP, NULL)) |
413 | return -11; | 410 | return -11; |
414 | 411 | ||
415 | (*(volatile unsigned long *) (SD_BASE+0x18)) &= ~(0x10001); | 412 | MCI_CTYPE &= ~(0x10001); |
416 | (*(volatile unsigned long *) (SD_BASE+0x18)) |= 0x1; | 413 | MCI_CTYPE |= 0x1; |
417 | 414 | ||
418 | if(!send_cmd(SD_SELECT_CARD, card_info.rca, MCI_NO_RESP, NULL)) | 415 | if(!send_cmd(SD_SELECT_CARD, card_info.rca, MCI_NO_RESP, NULL)) |
419 | return -9; | 416 | return -9; |
@@ -474,36 +471,36 @@ static void sd_thread(void) | |||
474 | 471 | ||
475 | static void init_controller(void) | 472 | static void init_controller(void) |
476 | { | 473 | { |
477 | int tmp = (*(volatile unsigned long *) (SD_BASE+0x70)); | 474 | int tmp = MCI_HCON; |
478 | int shift = 1 + ((tmp << 26) >> 27); | 475 | int shift = 1 + ((tmp << 26) >> 27); |
479 | 476 | ||
480 | (*(volatile unsigned long *) (SD_BASE+0x04)) &= ~((1 << shift) -1); | 477 | MCI_PWREN &= ~((1 << shift) -1); |
481 | (*(volatile unsigned long *) (SD_BASE+0x04)) = (1 << shift) -1; | 478 | MCI_PWREN = (1 << shift) -1; |
482 | 479 | ||
483 | mci_delay(); | 480 | mci_delay(); |
484 | 481 | ||
485 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 1; | 482 | MCI_CTRL |= 1; |
486 | int max = 1000; | 483 | int max = 1000; |
487 | while(max-- && !(*(volatile unsigned long *) (SD_BASE+0x00)) & 1) | 484 | while(max-- && !(MCI_CTRL & 1)) |
488 | ; | 485 | ; |
489 | 486 | ||
490 | MCI_CLEAR = 0xffffffff; | 487 | MCI_RAW_STATUS = 0xffffffff; |
491 | MCI_MASK = 0xffffbffe; | 488 | MCI_MASK = 0xffffbffe; |
492 | 489 | ||
493 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x10; | 490 | MCI_CTRL |= 0x10; |
494 | (*(volatile unsigned long *) (SD_BASE+0x14)) = 0xffffffff; | 491 | MCI_TMOUT = 0xffffffff; |
495 | 492 | ||
496 | (*(volatile unsigned long *) (SD_BASE+0x10)) = (1<<shift) - 1; | 493 | MCI_CLKENA = (1<<shift) - 1; |
497 | 494 | ||
498 | MCI_ARGUMENT = 0; | 495 | MCI_ARGUMENT = 0; |
499 | MCI_COMMAND = 0x80202000; | 496 | MCI_COMMAND = 0x80202000; |
500 | max = 10; | 497 | max = 10; |
501 | while(max-- && (MCI_COMMAND & (1<<31))) ; | 498 | while(max-- && (MCI_COMMAND & (1<<31))) ; |
502 | 499 | ||
503 | (*(volatile unsigned long *) (SD_BASE+0x64)) = 0xfffff; | 500 | MCI_DEBNCE = 0xfffff; |
504 | 501 | ||
505 | (*(volatile unsigned long *) (SD_BASE+0x4c)) = ~0x7fff0fff; // interrupt mask ? | 502 | MCI_FIFOTH = ~0x7fff0fff; |
506 | (*(volatile unsigned long *) (SD_BASE+0x4c)) |= 0x503f0080; | 503 | MCI_FIFOTH |= 0x503f0080; |
507 | 504 | ||
508 | MCI_MASK = 0xffffbffe; | 505 | MCI_MASK = 0xffffbffe; |
509 | } | 506 | } |
@@ -657,20 +654,20 @@ static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool w | |||
657 | write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK; | 654 | write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK; |
658 | 655 | ||
659 | 656 | ||
660 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 2; | 657 | MCI_CTRL |= 2; |
661 | while(( *(volatile unsigned long *) (SD_BASE+0x00)) & 2) ; | 658 | while(MCI_CTRL & 2) ; |
662 | 659 | ||
663 | //(*(volatile unsigned long *) (SD_BASE+0x1c)) = 512; | 660 | //MCI_BLKSIZ = 512; |
664 | (*(volatile unsigned long *) (SD_BASE+0x20)) = transfer * 512; | 661 | MCI_BYTCNT = transfer * 512; |
665 | 662 | ||
666 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 2; | 663 | MCI_CTRL |= 2; |
667 | while(( *(volatile unsigned long *) (SD_BASE+0x00)) & 2) ; | 664 | while(MCI_CTRL & 2) ; |
668 | 665 | ||
669 | (*(volatile unsigned long *) (SD_BASE+0x4c)) &= ~0x7fff0fff; | 666 | MCI_FIFOTH &= ~0x7fff0fff; |
670 | 667 | ||
671 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x20; | 668 | MCI_CTRL |= 0x20; |
672 | MCI_MASK = 0xBE8C; | 669 | MCI_MASK = 0xBE8C; |
673 | (*(volatile unsigned long *) (SD_BASE+0x4c)) |= 0x503f0080; | 670 | MCI_FIFOTH |= 0x503f0080; |
674 | 671 | ||
675 | 672 | ||
676 | if(card_info.ocr & (1<<30) ) /* SDHC */ | 673 | if(card_info.ocr & (1<<30) ) /* SDHC */ |