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authorRafaël Carré <rafael.carre@gmail.com>2008-12-01 04:07:13 +0000
committerRafaël Carré <rafael.carre@gmail.com>2008-12-01 04:07:13 +0000
commit50519416ca1c591f16fd4c59107e9c10eb4e2380 (patch)
treecb6207b0804717d99594864eafabfa8f8ca491a0 /firmware/target
parentc9ba3adf0ddef0ce55dd24e446b878e3de9ee058 (diff)
downloadrockbox-50519416ca1c591f16fd4c59107e9c10eb4e2380.tar.gz
rockbox-50519416ca1c591f16fd4c59107e9c10eb4e2380.zip
Sansa Clip : save one instruction per 8 pixels loop in lcd_grey_data
We set directly the needed bits to write into DBOP_DOUT (15:13 and 3:0) Since we can't set the mask 0xf00f with one mov instruction, revert the logic and use orrne instead of biceq (in the whole function for consistency) Fix suggested by Jens Arnold git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19279 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target')
-rw-r--r--firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S22
1 files changed, 12 insertions, 10 deletions
diff --git a/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S b/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S
index aab46861ba..0f68a2f664 100644
--- a/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S
+++ b/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S
@@ -59,32 +59,34 @@ lcd_grey_data:
59 ldmia r1, {r3-r4} /* Fetch 8 pixel phases */ 59 ldmia r1, {r3-r4} /* Fetch 8 pixel phases */
60 ldmia r0!, {r5-r6} /* Fetch 8 pixel values */ 60 ldmia r0!, {r5-r6} /* Fetch 8 pixel values */
61 61
62 mov r7, #0xff 62 mov r7, #0
63
64 /* set bits 15..12 */
63 tst r3, #0x80 65 tst r3, #0x80
64 biceq r7, r7, #0x80 66 orrne r7, r7, #0x8000
65 tst r3, #0x8000 67 tst r3, #0x8000
66 biceq r7, r7, #0x40 68 orrne r7, r7, #0x4000
67 tst r3, #0x800000 69 tst r3, #0x800000
68 biceq r7, r7, #0x20 70 orrne r7, r7, #0x2000
69 tst r3, #0x80000000 71 tst r3, #0x80000000
70 biceq r7, r7, #0x10 72 orrne r7, r7, #0x1000
71 bic r3, r3, r8 73 bic r3, r3, r8
72 add r3, r3, r5 74 add r3, r3, r5
73 75
76 /* set bits 3..0 */
74 tst r4, #0x80 77 tst r4, #0x80
75 biceq r7, r7, #0x08 78 orrne r7, r7, #0x08
76 tst r4, #0x8000 79 tst r4, #0x8000
77 biceq r7, r7, #0x04 80 orrne r7, r7, #0x04
78 tst r4, #0x800000 81 tst r4, #0x800000
79 biceq r7, r7, #0x02 82 orrne r7, r7, #0x02
80 tst r4, #0x80000000 83 tst r4, #0x80000000
81 biceq r7, r7, #0x01 84 orrne r7, r7, #0x01
82 bic r4, r4, r8 85 bic r4, r4, r8
83 add r4, r4, r6 86 add r4, r4, r6
84 87
85 stmia r1!, {r3-r4} 88 stmia r1!, {r3-r4}
86 89
87 orr r7, r7, r7, lsl #8 @ we set 15:13 to the MSb and 3:0 to the LSb
88 strh r7, [lr, #0x10] @ DBOP_DOUT 90 strh r7, [lr, #0x10] @ DBOP_DOUT
89 91
901: 921: