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author | Aidan MacDonald <amachronic@protonmail.com> | 2022-03-05 15:53:08 +0000 |
---|---|---|
committer | Aidan MacDonald <amachronic@protonmail.com> | 2022-03-25 21:36:51 +0000 |
commit | 2810c549a65327c1d42cdacdf16247d3211ab75c (patch) | |
tree | 2482ad1c7b64daf79a7ed001047fb75db454d754 /firmware/target | |
parent | 7cb49cfb33647941d4a706675832bfc57a4e27cf (diff) | |
download | rockbox-2810c549a65327c1d42cdacdf16247d3211ab75c.tar.gz rockbox-2810c549a65327c1d42cdacdf16247d3211ab75c.zip |
x1000: spl: remove dual boot support code
Removes the SPL's dual boot support code, and removes the dual
boot selection code on the M3K and Q1 since they can now do it
from the main bootloader.
Change-Id: Ie1b27e98c6ed4b3e37db86cfb485d6f3a6c5b25e
Diffstat (limited to 'firmware/target')
4 files changed, 0 insertions, 220 deletions
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c index cbbe8b1d5d..771082b2a7 100644 --- a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c | |||
@@ -24,21 +24,6 @@ | |||
24 | #include "spl-x1000.h" | 24 | #include "spl-x1000.h" |
25 | #include "gpio-x1000.h" | 25 | #include "gpio-x1000.h" |
26 | 26 | ||
27 | #define CMDLINE_COMMON \ | ||
28 | "mem=64M@0x0 no_console_suspend console=ttyS2,115200n8 lpj=5009408 ip=off" | ||
29 | #define CMDLINE_NORMAL \ | ||
30 | " init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw loglevel=8" | ||
31 | |||
32 | static int dualboot_setup(void) | ||
33 | { | ||
34 | spl_dualboot_init_clocktree(); | ||
35 | spl_dualboot_init_uart2(); | ||
36 | |||
37 | /* load PDMA MCU firmware */ | ||
38 | jz_writef(CPM_CLKGR, PDMA(0)); | ||
39 | return spl_storage_read(0x4000, 0x2000, (void*)0xb3422000); | ||
40 | } | ||
41 | |||
42 | const struct spl_boot_option spl_boot_options[] = { | 27 | const struct spl_boot_option spl_boot_options[] = { |
43 | [BOOT_OPTION_ROCKBOX] = { | 28 | [BOOT_OPTION_ROCKBOX] = { |
44 | .storage_addr = 0x6800, | 29 | .storage_addr = 0x6800, |
@@ -47,60 +32,10 @@ const struct spl_boot_option spl_boot_options[] = { | |||
47 | .exec_addr = X1000_DRAM_BASE, | 32 | .exec_addr = X1000_DRAM_BASE, |
48 | .flags = BOOTFLAG_UCLPACK, | 33 | .flags = BOOTFLAG_UCLPACK, |
49 | }, | 34 | }, |
50 | [BOOT_OPTION_OFW_PLAYER] = { | ||
51 | .storage_addr = 0x20000, | ||
52 | .storage_size = 4 * 1024 * 1024, | ||
53 | .load_addr = 0x80efffc0, | ||
54 | .exec_addr = 0x80f00000, | ||
55 | .cmdline = CMDLINE_COMMON CMDLINE_NORMAL, | ||
56 | .cmdline_addr = 0x80004000, | ||
57 | .setup = dualboot_setup, | ||
58 | }, | ||
59 | [BOOT_OPTION_OFW_RECOVERY] = { | ||
60 | .storage_addr = 0x420000, | ||
61 | .storage_size = 5 * 1024 * 1024, | ||
62 | .load_addr = 0x80efffc0, | ||
63 | .exec_addr = 0x80f00000, | ||
64 | .cmdline = CMDLINE_COMMON, | ||
65 | .cmdline_addr = 0x80004000, | ||
66 | .setup = dualboot_setup, | ||
67 | }, | ||
68 | }; | 35 | }; |
69 | 36 | ||
70 | int spl_get_boot_option(void) | 37 | int spl_get_boot_option(void) |
71 | { | 38 | { |
72 | /* Button debounce time in OST clock cycles */ | ||
73 | const uint32_t btn_stable_time = 100 * (X1000_EXCLK_FREQ / 4000); | ||
74 | |||
75 | /* Buttons to poll */ | ||
76 | const unsigned port = GPIO_A; | ||
77 | const uint32_t recov_pin = (1 << 19); /* Volume Up */ | ||
78 | const uint32_t orig_fw_pin = (1 << 17); /* Play */ | ||
79 | |||
80 | uint32_t pin = -1, lastpin = 0; | ||
81 | uint32_t deadline = 0; | ||
82 | int iter_count = 30; /* to avoid an infinite loop */ | ||
83 | |||
84 | /* set GPIOs to input state */ | ||
85 | gpioz_configure(port, recov_pin|orig_fw_pin, GPIOF_INPUT); | ||
86 | |||
87 | /* Poll until we get a stable reading */ | ||
88 | do { | ||
89 | lastpin = pin; | ||
90 | pin = ~REG_GPIO_PIN(port) & (recov_pin|orig_fw_pin); | ||
91 | if(pin != lastpin) { | ||
92 | deadline = __ost_read32() + btn_stable_time; | ||
93 | iter_count -= 1; | ||
94 | } | ||
95 | } while(iter_count > 0 && __ost_read32() < deadline); | ||
96 | |||
97 | if(iter_count >= 0 && (pin & orig_fw_pin)) { | ||
98 | if(pin & recov_pin) | ||
99 | return BOOT_OPTION_OFW_RECOVERY; | ||
100 | else | ||
101 | return BOOT_OPTION_OFW_PLAYER; | ||
102 | } | ||
103 | |||
104 | return BOOT_OPTION_ROCKBOX; | 39 | return BOOT_OPTION_ROCKBOX; |
105 | } | 40 | } |
106 | 41 | ||
diff --git a/firmware/target/mips/ingenic_x1000/shanlingq1/spl-shanlingq1.c b/firmware/target/mips/ingenic_x1000/shanlingq1/spl-shanlingq1.c index 33303c5e6b..c0cc7df0dd 100644 --- a/firmware/target/mips/ingenic_x1000/shanlingq1/spl-shanlingq1.c +++ b/firmware/target/mips/ingenic_x1000/shanlingq1/spl-shanlingq1.c | |||
@@ -24,21 +24,6 @@ | |||
24 | #include "spl-x1000.h" | 24 | #include "spl-x1000.h" |
25 | #include "gpio-x1000.h" | 25 | #include "gpio-x1000.h" |
26 | 26 | ||
27 | #define CMDLINE_COMMON \ | ||
28 | "mem=64M@0x0 no_console_suspend console=ttyS2,115200n8 lpj=5009408 ip=off" | ||
29 | #define CMDLINE_NORMAL \ | ||
30 | " init=/linuxrc ubi.mtd=5 root=ubi0:rootfs ubi.mtd=6 rootfstype=ubifs rw" | ||
31 | |||
32 | static int dualboot_setup(void) | ||
33 | { | ||
34 | spl_dualboot_init_clocktree(); | ||
35 | spl_dualboot_init_uart2(); | ||
36 | |||
37 | /* load PDMA MCU firmware */ | ||
38 | jz_writef(CPM_CLKGR, PDMA(0)); | ||
39 | return spl_storage_read(0x4000, 0x2000, (void*)0xb3422000); | ||
40 | } | ||
41 | |||
42 | const struct spl_boot_option spl_boot_options[] = { | 27 | const struct spl_boot_option spl_boot_options[] = { |
43 | [BOOT_OPTION_ROCKBOX] = { | 28 | [BOOT_OPTION_ROCKBOX] = { |
44 | .storage_addr = 0x6800, | 29 | .storage_addr = 0x6800, |
@@ -47,60 +32,10 @@ const struct spl_boot_option spl_boot_options[] = { | |||
47 | .exec_addr = X1000_DRAM_BASE, | 32 | .exec_addr = X1000_DRAM_BASE, |
48 | .flags = BOOTFLAG_UCLPACK, | 33 | .flags = BOOTFLAG_UCLPACK, |
49 | }, | 34 | }, |
50 | [BOOT_OPTION_OFW_PLAYER] = { | ||
51 | .storage_addr = 0x140000, | ||
52 | .storage_size = 8 * 1024 * 1024, | ||
53 | .load_addr = 0x80efffc0, | ||
54 | .exec_addr = 0x80f00000, | ||
55 | .cmdline = CMDLINE_COMMON CMDLINE_NORMAL, | ||
56 | .cmdline_addr = 0x80004000, | ||
57 | .setup = dualboot_setup, | ||
58 | }, | ||
59 | [BOOT_OPTION_OFW_RECOVERY] = { | ||
60 | .storage_addr = 0x940000, | ||
61 | .storage_size = 10 * 1024 * 1024, | ||
62 | .load_addr = 0x80efffc0, | ||
63 | .exec_addr = 0x80f00000, | ||
64 | .cmdline = CMDLINE_COMMON, | ||
65 | .cmdline_addr = 0x80004000, | ||
66 | .setup = dualboot_setup, | ||
67 | }, | ||
68 | }; | 35 | }; |
69 | 36 | ||
70 | int spl_get_boot_option(void) | 37 | int spl_get_boot_option(void) |
71 | { | 38 | { |
72 | /* Button debounce time in OST clock cycles */ | ||
73 | const uint32_t btn_stable_time = 100 * (X1000_EXCLK_FREQ / 4000); | ||
74 | |||
75 | /* Buttons to poll */ | ||
76 | const unsigned port = GPIO_B; | ||
77 | const uint32_t recov_pin = (1 << 22); /* Next */ | ||
78 | const uint32_t orig_fw_pin = (1 << 21); /* Prev */ | ||
79 | |||
80 | uint32_t pin = -1, lastpin = 0; | ||
81 | uint32_t deadline = 0; | ||
82 | int iter_count = 30; /* to avoid an infinite loop */ | ||
83 | |||
84 | /* set GPIOs to input state */ | ||
85 | gpioz_configure(port, recov_pin|orig_fw_pin, GPIOF_INPUT); | ||
86 | |||
87 | /* Poll until we get a stable reading */ | ||
88 | do { | ||
89 | lastpin = pin; | ||
90 | pin = ~REG_GPIO_PIN(port) & (recov_pin|orig_fw_pin); | ||
91 | if(pin != lastpin) { | ||
92 | deadline = __ost_read32() + btn_stable_time; | ||
93 | iter_count -= 1; | ||
94 | } | ||
95 | } while(iter_count > 0 && __ost_read32() < deadline); | ||
96 | |||
97 | if(iter_count >= 0 && (pin & orig_fw_pin)) { | ||
98 | if(pin & recov_pin) | ||
99 | return BOOT_OPTION_OFW_RECOVERY; | ||
100 | else | ||
101 | return BOOT_OPTION_OFW_PLAYER; | ||
102 | } | ||
103 | |||
104 | return BOOT_OPTION_ROCKBOX; | 39 | return BOOT_OPTION_ROCKBOX; |
105 | } | 40 | } |
106 | 41 | ||
diff --git a/firmware/target/mips/ingenic_x1000/spl-x1000.c b/firmware/target/mips/ingenic_x1000/spl-x1000.c index ac3a17f69f..1abbdcd7a4 100644 --- a/firmware/target/mips/ingenic_x1000/spl-x1000.c +++ b/firmware/target/mips/ingenic_x1000/spl-x1000.c | |||
@@ -55,92 +55,6 @@ void* spl_alloc(size_t count) | |||
55 | return heap; | 55 | return heap; |
56 | } | 56 | } |
57 | 57 | ||
58 | /* Used by: | ||
59 | * - FiiO M3K | ||
60 | * - Shanling Q1 | ||
61 | * | ||
62 | * Amend it and add #ifdefs for other targets if needed. | ||
63 | */ | ||
64 | void spl_dualboot_init_clocktree(void) | ||
65 | { | ||
66 | /* Make sure these are gated to match the OF behavior. */ | ||
67 | jz_writef(CPM_CLKGR, PCM(1), MAC(1), LCD(1), MSC0(1), MSC1(1), OTG(1), CIM(1)); | ||
68 | |||
69 | /* Set clock sources, and make sure every clock starts out stopped */ | ||
70 | jz_writef(CPM_I2SCDR, CS_V(EXCLK)); | ||
71 | jz_writef(CPM_PCMCDR, CS_V(EXCLK)); | ||
72 | |||
73 | jz_writef(CPM_MACCDR, CLKSRC_V(MPLL), CE(1), STOP(1), CLKDIV(0xfe)); | ||
74 | while(jz_readf(CPM_MACCDR, BUSY)); | ||
75 | |||
76 | jz_writef(CPM_LPCDR, CLKSRC_V(MPLL), CE(1), STOP(1), CLKDIV(0xfe)); | ||
77 | while(jz_readf(CPM_LPCDR, BUSY)); | ||
78 | |||
79 | jz_writef(CPM_MSC0CDR, CLKSRC_V(MPLL), CE(1), STOP(1), CLKDIV(0xfe)); | ||
80 | while(jz_readf(CPM_MSC0CDR, BUSY)); | ||
81 | |||
82 | jz_writef(CPM_MSC1CDR, CE(1), STOP(1), CLKDIV(0xfe)); | ||
83 | while(jz_readf(CPM_MSC1CDR, BUSY)); | ||
84 | |||
85 | jz_writef(CPM_CIMCDR, CLKSRC_V(MPLL), CE(1), STOP(1), CLKDIV(0xfe)); | ||
86 | while(jz_readf(CPM_CIMCDR, BUSY)); | ||
87 | |||
88 | jz_writef(CPM_USBCDR, CLKSRC_V(EXCLK), CE(1), STOP(1)); | ||
89 | while(jz_readf(CPM_USBCDR, BUSY)); | ||
90 | } | ||
91 | |||
92 | void spl_dualboot_init_uart2(void) | ||
93 | { | ||
94 | /* Ungate the clock and select UART2 device function */ | ||
95 | jz_writef(CPM_CLKGR, UART2(0)); | ||
96 | gpioz_configure(GPIO_C, 3 << 30, GPIOF_DEVICE(1)); | ||
97 | |||
98 | /* Disable all interrupts */ | ||
99 | jz_write(UART_UIER(2), 0); | ||
100 | |||
101 | /* FIFO configuration */ | ||
102 | jz_overwritef(UART_UFCR(2), | ||
103 | RDTR(3), /* FIFO trigger level = 60? */ | ||
104 | UME(0), /* UART module disable */ | ||
105 | DME(1), /* DMA mode enable? */ | ||
106 | TFRT(1), /* transmit FIFO reset */ | ||
107 | RFRT(1), /* receive FIFO reset */ | ||
108 | FME(1)); /* FIFO mode enable */ | ||
109 | |||
110 | /* IR mode configuration */ | ||
111 | jz_overwritef(UART_ISR(2), | ||
112 | RDPL(1), /* Zero is negative pulse for receive */ | ||
113 | TDPL(1), /* ... and for transmit */ | ||
114 | XMODE(1), /* Pulse width 1.6us */ | ||
115 | RCVEIR(0), /* Disable IR for recieve */ | ||
116 | XMITIR(0)); /* ... and for transmit */ | ||
117 | |||
118 | /* Line configuration */ | ||
119 | jz_overwritef(UART_ULCR(2), DLAB(0), | ||
120 | WLS_V(8BITS), /* 8 bit words */ | ||
121 | SBLS_V(1_STOP_BIT), /* 1 stop bit */ | ||
122 | PARE(0), /* no parity */ | ||
123 | SBK(0)); /* don't set break */ | ||
124 | |||
125 | /* Set the baud rate... not too sure how this works. (Docs unclear!) */ | ||
126 | const unsigned divisor = 0x0004; | ||
127 | jz_writef(UART_ULCR(2), DLAB(1)); | ||
128 | jz_write(UART_UDLHR(2), (divisor >> 8) & 0xff); | ||
129 | jz_write(UART_UDLLR(2), divisor & 0xff); | ||
130 | jz_write(UART_UMR(2), 16); | ||
131 | jz_write(UART_UACR(2), 0); | ||
132 | jz_writef(UART_ULCR(2), DLAB(0)); | ||
133 | |||
134 | /* Enable UART */ | ||
135 | jz_overwritef(UART_UFCR(2), | ||
136 | RDTR(0), /* FIFO trigger level = 1 */ | ||
137 | DME(0), /* DMA mode disable */ | ||
138 | UME(1), /* UART module enable */ | ||
139 | TFRT(1), /* transmit FIFO reset */ | ||
140 | RFRT(1), /* receive FIFO reset */ | ||
141 | FME(1)); /* FIFO mode enable */ | ||
142 | } | ||
143 | |||
144 | static void init_ost(void) | 58 | static void init_ost(void) |
145 | { | 59 | { |
146 | /* NOTE: the prescaler needs to be the same as in system-x1000.c */ | 60 | /* NOTE: the prescaler needs to be the same as in system-x1000.c */ |
diff --git a/firmware/target/mips/ingenic_x1000/spl-x1000.h b/firmware/target/mips/ingenic_x1000/spl-x1000.h index 6d60dbf880..40ea97a5b8 100644 --- a/firmware/target/mips/ingenic_x1000/spl-x1000.h +++ b/firmware/target/mips/ingenic_x1000/spl-x1000.h | |||
@@ -58,10 +58,6 @@ extern int spl_storage_open(void); | |||
58 | extern void spl_storage_close(void); | 58 | extern void spl_storage_close(void); |
59 | extern int spl_storage_read(uint32_t addr, uint32_t length, void* buffer); | 59 | extern int spl_storage_read(uint32_t addr, uint32_t length, void* buffer); |
60 | 60 | ||
61 | /* Helpers for dual-booting with the Ingenic Linux OF */ | ||
62 | extern void spl_dualboot_init_clocktree(void); | ||
63 | extern void spl_dualboot_init_uart2(void); | ||
64 | |||
65 | /* Get the boot option selected by the user, eg. by a key press */ | 61 | /* Get the boot option selected by the user, eg. by a key press */ |
66 | extern int spl_get_boot_option(void); | 62 | extern int spl_get_boot_option(void); |
67 | 63 | ||