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author | Aidan MacDonald <amachronic@protonmail.com> | 2022-03-05 17:46:58 +0000 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2022-03-25 21:36:51 +0000 |
commit | 5d0f697e87da01f5fe66d2e76af77b9bcdc6bbbc (patch) | |
tree | 7af09b65939db5a7b4a688236154fabf6f4b33af /firmware/target/mips/ingenic_x1000/clk-x1000.c | |
parent | 3ae4a98e3bbe4f2c449e614cda67efea129f16b1 (diff) | |
download | rockbox-5d0f697e87da01f5fe66d2e76af77b9bcdc6bbbc.tar.gz rockbox-5d0f697e87da01f5fe66d2e76af77b9bcdc6bbbc.zip |
x1000: remove the last vestiges of boot option support
There should be no need for any compatibility hacks since this
value was mostly used internally between the SPL and bootloader.
clk_init() was the only user in the main Rockbox binary which
accessed it, but when loaded by the Rockbox bootloader that code
will not be reached since BOOT_FLAG_CLK_INIT is already set.
Change-Id: Idd68b9834172e652b47432bfb1e00c923ea35407
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/clk-x1000.c')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/clk-x1000.c | 59 |
1 files changed, 28 insertions, 31 deletions
diff --git a/firmware/target/mips/ingenic_x1000/clk-x1000.c b/firmware/target/mips/ingenic_x1000/clk-x1000.c index 4988e7c3bf..e3b0f792bb 100644 --- a/firmware/target/mips/ingenic_x1000/clk-x1000.c +++ b/firmware/target/mips/ingenic_x1000/clk-x1000.c | |||
@@ -265,39 +265,36 @@ void clk_init(void) | |||
265 | jz_writef(CPM_APCR, BS(1), PLLM(42 - 1), PLLN(0), PLLOD(0), ENABLE(1)); | 265 | jz_writef(CPM_APCR, BS(1), PLLM(42 - 1), PLLN(0), PLLOD(0), ENABLE(1)); |
266 | while(jz_readf(CPM_APCR, ON) == 0); | 266 | while(jz_readf(CPM_APCR, ON) == 0); |
267 | 267 | ||
268 | #if (defined(FIIO_M3K) || defined(EROS_QN)) | 268 | #if defined(FIIO_M3K) || defined(EROS_QN) |
269 | /* TODO: Allow targets to define their clock frequencies in their config, | 269 | /* TODO: Allow targets to define their clock frequencies in their config, |
270 | * instead of having this be a random special case. */ | 270 | * instead of having this be a random special case. */ |
271 | if(get_boot_option() == BOOT_OPTION_ROCKBOX) { | 271 | clk_set_ccr_div(CLKDIV_CPU(1) | /* 1008 MHz */ |
272 | clk_set_ccr_div(CLKDIV_CPU(1) | /* 1008 MHz */ | 272 | CLKDIV_L2(2) | /* 504 MHz */ |
273 | CLKDIV_L2(2) | /* 504 MHz */ | 273 | CLKDIV_AHB0(5) | /* 201.6 MHz */ |
274 | CLKDIV_AHB0(5) | /* 201.6 MHz */ | 274 | CLKDIV_AHB2(5) | /* 201.6 MHz */ |
275 | CLKDIV_AHB2(5) | /* 201.6 MHz */ | 275 | CLKDIV_PCLK(10)); /* 100.8 MHz */ |
276 | CLKDIV_PCLK(10)); /* 100.8 MHz */ | 276 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | |
277 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | | 277 | CLKMUX_CPU(SCLK_A) | |
278 | CLKMUX_CPU(SCLK_A) | | 278 | CLKMUX_AHB0(SCLK_A) | |
279 | CLKMUX_AHB0(SCLK_A) | | 279 | CLKMUX_AHB2(SCLK_A)); |
280 | CLKMUX_AHB2(SCLK_A)); | 280 | |
281 | 281 | /* DDR to 201.6 MHz */ | |
282 | /* DDR to 201.6 MHz */ | 282 | clk_set_ddr(X1000_CLK_SCLK_A, 5); |
283 | clk_set_ddr(X1000_CLK_SCLK_A, 5); | 283 | |
284 | 284 | /* Disable MPLL */ | |
285 | /* Disable MPLL */ | 285 | jz_writef(CPM_MPCR, ENABLE(0)); |
286 | jz_writef(CPM_MPCR, ENABLE(0)); | 286 | while(jz_readf(CPM_MPCR, ON)); |
287 | while(jz_readf(CPM_MPCR, ON)); | 287 | #else |
288 | } else { | 288 | /* Default configuration matching the Ingenic OF */ |
289 | #endif | 289 | clk_set_ccr_div(CLKDIV_CPU(1) | /* 1008 MHz */ |
290 | clk_set_ccr_div(CLKDIV_CPU(1) | /* 1008 MHz */ | 290 | CLKDIV_L2(2) | /* 504 MHz */ |
291 | CLKDIV_L2(2) | /* 504 MHz */ | 291 | CLKDIV_AHB0(3) | /* 200 MHz */ |
292 | CLKDIV_AHB0(3) | /* 200 MHz */ | 292 | CLKDIV_AHB2(3) | /* 200 MHz */ |
293 | CLKDIV_AHB2(3) | /* 200 MHz */ | 293 | CLKDIV_PCLK(6)); /* 100 MHz */ |
294 | CLKDIV_PCLK(6)); /* 100 MHz */ | 294 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | |
295 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | | 295 | CLKMUX_CPU(SCLK_A) | |
296 | CLKMUX_CPU(SCLK_A) | | 296 | CLKMUX_AHB0(MPLL) | |
297 | CLKMUX_AHB0(MPLL) | | 297 | CLKMUX_AHB2(MPLL)); |
298 | CLKMUX_AHB2(MPLL)); | ||
299 | #if (defined(FIIO_M3K) || defined(EROS_QN)) | ||
300 | } | ||
301 | #endif | 298 | #endif |
302 | 299 | ||
303 | /* mark that clocks have been initialized */ | 300 | /* mark that clocks have been initialized */ |