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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-05-03 13:43:26 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-05-03 13:43:26 +0000 |
commit | a6b31f18c89029c6f19609dc39cbb0abc59daeed (patch) | |
tree | 31c42391fd7b0a20c3203989ef9d7d776d0d7af4 /firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c | |
parent | ea664e06476cb572bab2eadbb9c060902a95a34a (diff) | |
download | rockbox-a6b31f18c89029c6f19609dc39cbb0abc59daeed.tar.gz rockbox-a6b31f18c89029c6f19609dc39cbb0abc59daeed.zip |
1) add support for ata-as-arm
2) remove obsolete audio-creativezvm.c
3) fix registers in i2c-dm320.c
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17316 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c | 102 |
1 files changed, 88 insertions, 14 deletions
diff --git a/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c index 331803360f..252239b62b 100644 --- a/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c +++ b/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c | |||
@@ -25,11 +25,18 @@ | |||
25 | #include "power.h" | 25 | #include "power.h" |
26 | #include "panic.h" | 26 | #include "panic.h" |
27 | #include "ata-target.h" | 27 | #include "ata-target.h" |
28 | #include "dm320.h" | ||
29 | |||
30 | void sleep_ms(int ms) | ||
31 | { | ||
32 | sleep(ms*HZ/1000); | ||
33 | } | ||
28 | 34 | ||
29 | void ide_power_enable(bool on) | 35 | void ide_power_enable(bool on) |
30 | { | 36 | { |
37 | /* Disabled until figured out what's wrong */ | ||
31 | #if 0 | 38 | #if 0 |
32 | IO_INTC_EINT1 &= ~INTR_EINT1_EXT2; | 39 | int old_level = disable_irq_save(); |
33 | if(on) | 40 | if(on) |
34 | { | 41 | { |
35 | IO_GIO_BITSET0 = (1 << 14); | 42 | IO_GIO_BITSET0 = (1 << 14); |
@@ -37,8 +44,7 @@ void ide_power_enable(bool on) | |||
37 | } | 44 | } |
38 | else | 45 | else |
39 | IO_GIO_BITCLR0 = (1 << 14); | 46 | IO_GIO_BITCLR0 = (1 << 14); |
40 | IO_INTC_EINT1 |= INTR_EINT1_EXT2; | 47 | restore_irq(old_level); |
41 | return; | ||
42 | #else | 48 | #else |
43 | (void)on; | 49 | (void)on; |
44 | #endif | 50 | #endif |
@@ -55,26 +61,24 @@ inline bool ide_powered() | |||
55 | 61 | ||
56 | void ata_reset(void) | 62 | void ata_reset(void) |
57 | { | 63 | { |
58 | /* Disabled until figured out what's wrong */ | 64 | int old_level = disable_irq_save(); |
59 | IO_INTC_EINT1 &= ~INTR_EINT1_EXT2; /*disable GIO2 interrupt */ | ||
60 | if(!ide_powered()) | 65 | if(!ide_powered()) |
61 | { | 66 | { |
62 | ide_power_enable(true); | 67 | ide_power_enable(true); |
63 | sleep(150); | 68 | sleep_ms(150); |
64 | } | 69 | } |
65 | else | 70 | else |
66 | { | 71 | { |
67 | IO_GIO_BITSET0 = (1 << 5); | 72 | IO_GIO_BITSET0 = (1 << 5); |
68 | IO_GIO_BITCLR0 = (1 << 3); | 73 | IO_GIO_BITCLR0 = (1 << 3); |
69 | sleep(1); | 74 | sleep_ms(1); |
70 | } | 75 | } |
71 | IO_GIO_BITCLR0 = (1 << 5); | 76 | IO_GIO_BITCLR0 = (1 << 5); |
72 | sleep(10); | 77 | sleep_ms(10); |
73 | IO_GIO_BITSET0 = (1 << 3); | 78 | IO_GIO_BITSET0 = (1 << 3); |
74 | while(!(ATA_COMMAND & STATUS_RDY)) | 79 | while(!(ATA_COMMAND & STATUS_RDY)) |
75 | sleep(10); | 80 | sleep_ms(10); |
76 | IO_INTC_EINT1 |= INTR_EINT1_EXT2; //enable GIO2 interrupt | 81 | restore_irq(old_level); |
77 | return; | ||
78 | } | 82 | } |
79 | 83 | ||
80 | void ata_enable(bool on) | 84 | void ata_enable(bool on) |
@@ -88,9 +92,79 @@ bool ata_is_coldstart(void) | |||
88 | return true; | 92 | return true; |
89 | } | 93 | } |
90 | 94 | ||
95 | #if 0 /* Disabled as device crashes; probably due to SDRAM addresses aren't 32-bit aligned */ | ||
96 | #define CS1_START 0x50000000 | ||
97 | #define DEST_ADDR (ATA_IOBASE-CS1_START) | ||
98 | static struct wakeup transfer_completion_signal; | ||
99 | |||
100 | void MTC0(void) | ||
101 | { | ||
102 | IO_INTC_IRQ1 = 1 << IRQ_MTC0; | ||
103 | wakeup_signal(&transfer_completion_signal); | ||
104 | } | ||
105 | |||
106 | void copy_read_sectors(unsigned char* buf, int wordcount) | ||
107 | { | ||
108 | bool lasthalfword = false; | ||
109 | unsigned short tmp; | ||
110 | if(wordcount < 16) | ||
111 | { | ||
112 | _copy_read_sectors(buf, wordcount); | ||
113 | return; | ||
114 | } | ||
115 | else if((unsigned long)buf % 32) /* Not 32-byte aligned */ | ||
116 | { | ||
117 | unsigned char* bufend = buf + ((unsigned long)buf % 32); | ||
118 | if( ((unsigned long)buf % 32) % 2 ) | ||
119 | lasthalfword = true; | ||
120 | wordcount -= ((unsigned long)buf % 32) / 2; | ||
121 | do | ||
122 | { | ||
123 | tmp = ATA_DATA; | ||
124 | *buf++ = tmp >> 8; | ||
125 | *buf++ = tmp & 0xff; | ||
126 | } while (buf < bufend); /* tail loop is faster */ | ||
127 | } | ||
128 | IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */ | ||
129 | IO_EMIF_AHBADDH = ((unsigned)buf >> 16) & ~(1 << 15); /* Set variable address */ | ||
130 | IO_EMIF_AHBADDL = (unsigned)buf & 0xFFFF; | ||
131 | IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */ | ||
132 | IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */ | ||
133 | IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF; | ||
134 | IO_EMIF_DMASIZE = wordcount*2; | ||
135 | IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */ | ||
136 | //wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | ||
137 | while(IO_EMIF_DMACTL & 1) | ||
138 | nop; | ||
139 | if(lasthalfword) | ||
140 | { | ||
141 | *buf += wordcount * 2; | ||
142 | tmp = ATA_DATA; | ||
143 | *buf++ = tmp >> 8; | ||
144 | *buf++ = tmp & 0xff; | ||
145 | } | ||
146 | } | ||
147 | void copy_write_sectors(const unsigned char* buf, int wordcount) | ||
148 | { | ||
149 | IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */ | ||
150 | IO_SDRAM_SDDMASEL = 0x0820; /* Temporarily set to standard value */ | ||
151 | IO_EMIF_AHBADDH = ((int)buf >> 16) & ~(1 << 15); /* Set variable address */ | ||
152 | IO_EMIF_AHBADDL = (int)buf & 0xFFFF; | ||
153 | IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */ | ||
154 | IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF; | ||
155 | IO_EMIF_DMASIZE = wordcount; | ||
156 | IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */ | ||
157 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | ||
158 | } | ||
159 | #endif | ||
160 | |||
91 | void ata_device_init(void) | 161 | void ata_device_init(void) |
92 | { | 162 | { |
93 | IO_INTC_EINT1 |= INTR_EINT1_EXT2; //enable GIO2 interrupt | 163 | IO_INTC_EINT1 |= INTR_EINT1_EXT2; /* enable GIO2 interrupt */ |
164 | #if 0 | ||
165 | IO_INTC_EINT1 |= 1 << IRQ_MTC0; /* enable MTC interrupt */ | ||
166 | wakeup_init(&transfer_completion_signal); | ||
167 | #endif | ||
94 | //TODO: mimic OF inits... | 168 | //TODO: mimic OF inits... |
95 | return; | 169 | return; |
96 | } | 170 | } |
@@ -98,8 +172,8 @@ void ata_device_init(void) | |||
98 | void GIO2(void) | 172 | void GIO2(void) |
99 | { | 173 | { |
100 | #ifdef DEBUG | 174 | #ifdef DEBUG |
101 | //printf("GIO2 interrupt..."); | 175 | logf("GIO2 interrupt..."); |
102 | #endif | 176 | #endif |
103 | IO_INTC_IRQ1 = INTR_IRQ1_EXT2; //Mask GIO2 interrupt | 177 | IO_INTC_IRQ1 = INTR_IRQ1_EXT2; /* Mask GIO2 interrupt */ |
104 | return; | 178 | return; |
105 | } | 179 | } |