Add some CACHEALIGN_* macros and a helper function to assist in aligning data and buffers on PortalPlayer processors to cache line boundaries. They're noops when PROC_NEED_CACHEALIGN isn't defined. Go safe and increase the value to 32 since I'm not sure yet if 16 is sufficient - changing that is a one-liner. Add helper to plugin API which will be needed shortly.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15523 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 7 insertions, 1 deletions

diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 6e433be9d5..e9419b3f86 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -94,11 +94,17 @@ static inline unsigned int processor_id(void)
 #define UNCACHED_ADDR(a) (a)
 #else
 #define UNCACHED_ADDR(a) \
-    ((typeof (a))((uintptr_t)(a) + 0x10000000))
+    ((typeof (a))((uintptr_t)(a) | 0x10000000))
 #endif
 
 #ifdef CPU_PP502x
 
+/* Certain data needs to be out of the way of cache line interference
+ * such as data for COP use or for use with UNCACHED_ADDR */
+#define PROC_NEEDS_CACHEALIGN
+#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
+
+/** cache functions **/
 #ifndef BOOTLOADER
 #define CACHE_FUNCTIONS_AS_CALL