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authorJens Arnold <amiconn@rockbox.org>2007-07-07 05:58:29 +0000
committerJens Arnold <amiconn@rockbox.org>2007-07-07 05:58:29 +0000
commitc6437185b7a5331d7d36a440ad67d3c7cd3502f4 (patch)
treecf1158b698802ca66432819b5dda9d88a893669f /firmware/target/arm/system-pp502x.c
parent68f975be8524e89fe582b20f3231f161b6f85e26 (diff)
downloadrockbox-c6437185b7a5331d7d36a440ad67d3c7cd3502f4.tar.gz
rockbox-c6437185b7a5331d7d36a440ad67d3c7cd3502f4.zip
Stop the crashes on some PP5022C targets (iPod Video, perhaps also Nano) introduced by the recent clock setup changes. Looks like some revisions of the chip don't reset the PLL_locked bit immediately after PLL setup.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13810 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-pp502x.c')
-rw-r--r--firmware/target/arm/system-pp502x.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index 4542913d53..4fca84600b 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -175,7 +175,7 @@ void set_cpu_frequency(long frequency)
175 outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020); 175 outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020);
176 176
177 outl(unknown2 & 0x3fffffff, 0x600060a0); 177 outl(unknown2 & 0x3fffffff, 0x600060a0);
178 178
179 unknown1 = (138 * postmult + 255) >> 8; 179 unknown1 = (138 * postmult + 255) >> 8;
180 if (unknown1 > 15) 180 if (unknown1 > 15)
181 unknown1 = 15; 181 unknown1 = 15;
@@ -189,9 +189,10 @@ void set_cpu_frequency(long frequency)
189 outl(pll_control, 0x60006034); 189 outl(pll_control, 0x60006034);
190 udelay(500); /* wait for relock */ 190 udelay(500); /* wait for relock */
191# else /* PP5022, PP5024 */ 191# else /* PP5022, PP5024 */
192 udelay(250);
192 while (!(inl(0x6000603c) & 0x80000000)); /* wait for relock */ 193 while (!(inl(0x6000603c) & 0x80000000)); /* wait for relock */
193# endif 194# endif
194 195
195 /* Select PLL as clock source? */ 196 /* Select PLL as clock source? */
196 outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020); 197 outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
197 198