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author | Jens Arnold <amiconn@rockbox.org> | 2007-11-08 06:52:48 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2007-11-08 06:52:48 +0000 |
commit | a50a80e1a3bcff9e3c739d796605c10e1f8e8d05 (patch) | |
tree | af615b3db3d9561bb8509feaf77fce68dc902f7c /firmware/target/arm/system-pp502x.c | |
parent | 57d71e4267ecf66c84173f8ff3606091187b93b1 (diff) | |
download | rockbox-a50a80e1a3bcff9e3c739d796605c10e1f8e8d05.tar.gz rockbox-a50a80e1a3bcff9e3c739d796605c10e1f8e8d05.zip |
Mini 2nd Gen: Almost doubled LCD update speed when not boosted (68.5->129fps @30MHz) by handling the serial LCD clock divider.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15524 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-pp502x.c')
-rw-r--r-- | firmware/target/arm/system-pp502x.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index 0f24997451..a1c4d1639e 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c | |||
@@ -178,6 +178,9 @@ static void pp_set_cpu_frequency(long frequency) | |||
178 | case CPUFREQ_MAX: | 178 | case CPUFREQ_MAX: |
179 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ | 179 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ |
180 | DEV_TIMING1 = 0x00000303; | 180 | DEV_TIMING1 = 0x00000303; |
181 | #ifdef IPOD_MINI2G | ||
182 | MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */ | ||
183 | #endif | ||
181 | #if CONFIG_CPU == PP5020 | 184 | #if CONFIG_CPU == PP5020 |
182 | PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ | 185 | PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ |
183 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ | 186 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ |
@@ -196,6 +199,9 @@ static void pp_set_cpu_frequency(long frequency) | |||
196 | case CPUFREQ_NORMAL: | 199 | case CPUFREQ_NORMAL: |
197 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ | 200 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ |
198 | DEV_TIMING1 = 0x00000303; | 201 | DEV_TIMING1 = 0x00000303; |
202 | #ifdef IPOD_MINI2G | ||
203 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | ||
204 | #endif | ||
199 | #if CONFIG_CPU == PP5020 | 205 | #if CONFIG_CPU == PP5020 |
200 | PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ | 206 | PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ |
201 | scale_suspend_core(false); | 207 | scale_suspend_core(false); |
@@ -220,6 +226,9 @@ static void pp_set_cpu_frequency(long frequency) | |||
220 | default: | 226 | default: |
221 | CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ | 227 | CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ |
222 | DEV_TIMING1 = 0x00000303; | 228 | DEV_TIMING1 = 0x00000303; |
229 | #ifdef IPOD_MINI2G | ||
230 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | ||
231 | #endif | ||
223 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | 232 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ |
224 | cpu_frequency = CPUFREQ_DEFAULT; | 233 | cpu_frequency = CPUFREQ_DEFAULT; |
225 | PROC_CTL(CURRENT_CORE) = 0x4800001f; nop; | 234 | PROC_CTL(CURRENT_CORE) = 0x4800001f; nop; |