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author | Michael Sparmann <theseven@rockbox.org> | 2010-11-14 15:18:05 +0000 |
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committer | Michael Sparmann <theseven@rockbox.org> | 2010-11-14 15:18:05 +0000 |
commit | b18d220e48e7e0678dd104ec04faaaa11303fb8a (patch) | |
tree | 831199694b4615848fa5c22ea84373725248f883 /firmware/target/arm/s5l8700 | |
parent | 316986df67ab75ab581007c41d64abcecef9801f (diff) | |
download | rockbox-b18d220e48e7e0678dd104ec04faaaa11303fb8a.tar.gz rockbox-b18d220e48e7e0678dd104ec04faaaa11303fb8a.zip |
iPod Nano 2G: Use sane (150 microseconds) PLL locking delays and properly set a third CLKCON register I just discovered
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28588 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s5l8700')
-rw-r--r-- | firmware/target/arm/s5l8700/crt0.S | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S index 5fd959cf91..bcd26ffcf7 100644 --- a/firmware/target/arm/s5l8700/crt0.S +++ b/firmware/target/arm/s5l8700/crt0.S | |||
@@ -136,9 +136,11 @@ start_loc: | |||
136 | ldr r0, =0x1ad200 // pdiv=0x1a, mdiv=0xd2 sdiv=0 | 136 | ldr r0, =0x1ad200 // pdiv=0x1a, mdiv=0xd2 sdiv=0 |
137 | #endif | 137 | #endif |
138 | str r0, [r1,#0x04] // PLL0PMS | 138 | str r0, [r1,#0x04] // PLL0PMS |
139 | ldr r0, =8100 | 139 | mov r0, #0 |
140 | str r0, [r1,#0x08] // PLL1PMS | ||
141 | ldr r0, =280 | ||
140 | str r0, [r1,#0x14] // PLL0LCNT | 142 | str r0, [r1,#0x14] // PLL0LCNT |
141 | mov r0, #1 | 143 | mov r0, #3 |
142 | str r0, [r1,#0x24] // PLLCON | 144 | str r0, [r1,#0x24] // PLLCON |
143 | 1: | 145 | 1: |
144 | ldr r0, [r1,#0x20] // PLLLOCK | 146 | ldr r0, [r1,#0x20] // PLLLOCK |
@@ -148,6 +150,8 @@ start_loc: | |||
148 | str r0, [r1,#0x3c] // CLKCON2 | 150 | str r0, [r1,#0x3c] // CLKCON2 |
149 | ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off | 151 | ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off |
150 | str r0, [r1] // CLKCON | 152 | str r0, [r1] // CLKCON |
153 | mov r0, #0x37 // SCLK = 25MHz | ||
154 | str r0, [r1,#0x10] // CLKCON3 | ||
151 | 155 | ||
152 | ldr r2, =0xc0000078 | 156 | ldr r2, =0xc0000078 |
153 | mrc 15, 0, r0, c1, c0, 0 | 157 | mrc 15, 0, r0, c1, c0, 0 |