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authorMichael Sparmann <theseven@rockbox.org>2009-10-11 13:48:12 +0000
committerMichael Sparmann <theseven@rockbox.org>2009-10-11 13:48:12 +0000
commit3b549fedbb1647bd6c8f010ff385e9aa27e538e3 (patch)
tree56fe54c907cead3208b1d8cc04967348037fac7f /firmware/target/arm/s5l8700
parente13c6001332882291363bdf2f1155875439fe187 (diff)
downloadrockbox-3b549fedbb1647bd6c8f010ff385e9aa27e538e3.tar.gz
rockbox-3b549fedbb1647bd6c8f010ff385e9aa27e538e3.zip
iPod Nano 2G: Reset NAND banks after powering the chip up.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23110 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s5l8700')
-rw-r--r--firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c80
1 files changed, 41 insertions, 39 deletions
diff --git a/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c b/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
index fe59fc5d2d..6289fbc66f 100644
--- a/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
+++ b/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
@@ -128,45 +128,6 @@ uint32_t nand_timeout(long timeout)
128 } 128 }
129} 129}
130 130
131void nand_power_up(void)
132{
133 unsigned char powerup[2] = {0x15, 1};
134 mutex_lock(&ecc_mtx);
135 PWRCONEXT &= ~0x40;
136 PWRCON &= ~0x100000;
137 PCON2 = 0x33333333;
138 PDAT2 = 0;
139 PCON3 = 0x11113333;
140 PDAT3 = 0;
141 PCON4 = 0x33333333;
142 PDAT4 = 0;
143 PCON5 = (PCON5 & ~0xF) | 3;
144 PUNK5 = 1;
145 pmu_write_multiple(0x35, 2, powerup);
146 sleep(HZ / 50);
147 nand_powered = 1;
148 mutex_unlock(&ecc_mtx);
149}
150
151void nand_power_down(void)
152{
153 unsigned char powerdown[2] = {0x15, 0};
154 mutex_lock(&ecc_mtx);
155 pmu_write_multiple(0x35, 2, powerdown);
156 PCON2 = 0x11111111;
157 PDAT2 = 0;
158 PCON3 = 0x11111111;
159 PDAT3 = 0;
160 PCON4 = 0x11111111;
161 PDAT4 = 0;
162 PCON5 = (PCON5 & ~0xF) | 1;
163 PUNK5 = 1;
164 PWRCONEXT |= 0x40;
165 PWRCON |= 0x100000;
166 nand_powered = 0;
167 mutex_unlock(&ecc_mtx);
168}
169
170uint32_t nand_wait_rbbdone(void) 131uint32_t nand_wait_rbbdone(void)
171{ 132{
172 long timeout = current_tick + HZ / 50; 133 long timeout = current_tick + HZ / 50;
@@ -338,6 +299,47 @@ uint32_t nand_get_chip_type(uint32_t bank)
338 return nand_unlock(result); 299 return nand_unlock(result);
339} 300}
340 301
302void nand_power_up(void)
303{
304 unsigned char powerup[2] = {0x15, 1};
305 uint32_t i;
306 mutex_lock(&ecc_mtx);
307 PWRCONEXT &= ~0x40;
308 PWRCON &= ~0x100000;
309 PCON2 = 0x33333333;
310 PDAT2 = 0;
311 PCON3 = 0x11113333;
312 PDAT3 = 0;
313 PCON4 = 0x33333333;
314 PDAT4 = 0;
315 PCON5 = (PCON5 & ~0xF) | 3;
316 PUNK5 = 1;
317 pmu_write_multiple(0x35, 2, powerup);
318 sleep(HZ / 50);
319 for (i = 0; i < 4; i++) nand_reset(i);
320 nand_powered = 1;
321 mutex_unlock(&ecc_mtx);
322}
323
324void nand_power_down(void)
325{
326 unsigned char powerdown[2] = {0x15, 0};
327 mutex_lock(&ecc_mtx);
328 pmu_write_multiple(0x35, 2, powerdown);
329 PCON2 = 0x11111111;
330 PDAT2 = 0;
331 PCON3 = 0x11111111;
332 PDAT3 = 0;
333 PCON4 = 0x11111111;
334 PDAT4 = 0;
335 PCON5 = (PCON5 & ~0xF) | 1;
336 PUNK5 = 1;
337 PWRCONEXT |= 0x40;
338 PWRCON |= 0x100000;
339 nand_powered = 0;
340 mutex_unlock(&ecc_mtx);
341}
342
341uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer, 343uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
342 void* sparebuffer, uint32_t doecc, 344 void* sparebuffer, uint32_t doecc,
343 uint32_t checkempty) 345 uint32_t checkempty)