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authorMichael Sparmann <theseven@rockbox.org>2009-10-05 16:01:26 +0000
committerMichael Sparmann <theseven@rockbox.org>2009-10-05 16:01:26 +0000
commit271c67e802c65b243c7e4c76e276a893345f15fe (patch)
tree10e1389be74cfc62c0651a590c4496fb2e1fea34 /firmware/target/arm/s5l8700/timer-s5l8700.c
parent79bf2da1ef6f8f16c44ba8fa6d71ea6870a19767 (diff)
downloadrockbox-271c67e802c65b243c7e4c76e276a893345f15fe.tar.gz
rockbox-271c67e802c65b243c7e4c76e276a893345f15fe.zip
Fix the user timer on iPod Nano 2G
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22959 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s5l8700/timer-s5l8700.c')
-rw-r--r--firmware/target/arm/s5l8700/timer-s5l8700.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/firmware/target/arm/s5l8700/timer-s5l8700.c b/firmware/target/arm/s5l8700/timer-s5l8700.c
index 3e8e7d7ad4..9ae7e01565 100644
--- a/firmware/target/arm/s5l8700/timer-s5l8700.c
+++ b/firmware/target/arm/s5l8700/timer-s5l8700.c
@@ -35,10 +35,10 @@
35 TODO: investigate why the timer seems to count twice as fast as expected 35 TODO: investigate why the timer seems to count twice as fast as expected
36*/ 36*/
37 37
38void INT_TIMERD(void) 38void INT_TIMERC(void)
39{ 39{
40 /* clear interrupt */ 40 /* clear interrupt */
41 TDCON = TDCON; 41 TCCON = TCCON;
42 42
43 if (pfn_timer != NULL) { 43 if (pfn_timer != NULL) {
44 pfn_timer(); 44 pfn_timer();
@@ -52,7 +52,7 @@ bool timer_set(long cycles, bool start)
52 long count; 52 long count;
53 53
54 /* stop and clear timer */ 54 /* stop and clear timer */
55 TDCMD = (1 << 1); /* TD_CLR */ 55 TCCMD = (1 << 1); /* TD_CLR */
56 56
57 /* optionally unregister any previously registered timer user */ 57 /* optionally unregister any previously registered timer user */
58 if (start) { 58 if (start) {
@@ -78,27 +78,27 @@ bool timer_set(long cycles, bool start)
78 } 78 }
79 79
80 /* configure timer */ 80 /* configure timer */
81 TDCON = (1 << 12) | /* TD_INT0_EN */ 81 TCCON = (1 << 12) | /* TD_INT0_EN */
82 (cs << 8) | /* TS_CS */ 82 (cs << 8) | /* TS_CS */
83 (0 << 4); /* TD_MODE_SEL, 0 = interval mode */ 83 (0 << 4); /* TD_MODE_SEL, 0 = interval mode */
84 TDPRE = prescale - 1; 84 TCPRE = prescale - 1;
85 TDDATA0 = count; 85 TCDATA0 = count;
86 TDCMD = (1 << 0); /* TD_ENABLE */ 86 TCCMD = (1 << 0); /* TD_ENABLE */
87 87
88 /* enable interrupt */ 88 /* enable interrupt */
89 INTMSK |= (1 << 9); 89 INTMSK |= INTMSK_TIMERC;
90 90
91 return true; 91 return true;
92} 92}
93 93
94bool timer_start(void) 94bool timer_start(void)
95{ 95{
96 TDCMD = (1 << 0); /* TD_ENABLE */ 96 TCCMD = (1 << 0); /* TD_ENABLE */
97 return true; 97 return true;
98} 98}
99 99
100void timer_stop(void) 100void timer_stop(void)
101{ 101{
102 TDCMD = (0 << 0); /* TD_ENABLE */ 102 TCCMD = (0 << 0); /* TD_ENABLE */
103} 103}
104 104