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| author | Michael Sevakis <jethead71@rockbox.org> | 2010-05-04 10:07:53 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2010-05-04 10:07:53 +0000 |
| commit | 931e06de64100e28031627964321da3fdb449378 (patch) | |
| tree | 72a073d7ec3ede9554b394887d43d19fda6e8177 /firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h | |
| parent | 7480afb3c59f4aebff262e1ce47395a3924ca994 (diff) | |
| download | rockbox-931e06de64100e28031627964321da3fdb449378.tar.gz rockbox-931e06de64100e28031627964321da3fdb449378.zip | |
i.MX31/Gigabeat S: Actually enable DPTC which can set optimal voltage for 528MHz. Requires an SPI and PMIC interface rework because of the low-latency needs for the DPTC to work best with minimal panicing. SPI can work with multitasking and asynchronously from interrupt handlers or normal code.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25800 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h')
| -rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h b/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h index 2356e23252..4876736a2b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h | |||
| @@ -75,9 +75,6 @@ | |||
| 75 | /* Define mask of which reference circuits are employed for DPTC */ | 75 | /* Define mask of which reference circuits are employed for DPTC */ |
| 76 | #define DPTC_DRCE_MASK (CCM_PMCR0_DRCE1 | CCM_PMCR0_DRCE3) | 76 | #define DPTC_DRCE_MASK (CCM_PMCR0_DRCE1 | CCM_PMCR0_DRCE3) |
| 77 | 77 | ||
| 78 | /* When panicing, this working point is used */ | ||
| 79 | #define DPTC_PANIC_WP | ||
| 80 | |||
| 81 | /* Due to a hardware bug in chip revisions < 2.0, when switching between | 78 | /* Due to a hardware bug in chip revisions < 2.0, when switching between |
| 82 | * Serial and MCU PLLs, DVFS forces the target PLL to go into reset and | 79 | * Serial and MCU PLLs, DVFS forces the target PLL to go into reset and |
| 83 | * relock, only post divider frequency scaling is possible. | 80 | * relock, only post divider frequency scaling is possible. |