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author | Amaury Pouly <amaury.pouly@gmail.com> | 2012-01-21 20:14:27 +0100 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2012-01-21 20:15:29 +0100 |
commit | eaa83bd64775b87e943d345e2810deed44408776 (patch) | |
tree | 2d3eb4c5c29338c5bd254c1c54e8114d07cfc062 /firmware/target/arm/imx233 | |
parent | 6b7db7e465f03712520128b4a527829c5f2be3ca (diff) | |
download | rockbox-eaa83bd64775b87e943d345e2810deed44408776.tar.gz rockbox-eaa83bd64775b87e943d345e2810deed44408776.zip |
imx233: fix clkctrl code (some registers don't have a SET/CLR variant)
Change-Id: I3ce6a77cdc5ea89e1e43bc00c9ec43664e765fdc
Diffstat (limited to 'firmware/target/arm/imx233')
-rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.c | 17 | ||||
-rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.h | 5 |
2 files changed, 14 insertions, 8 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index dbdc12e38e..744a4b11d8 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c | |||
@@ -76,16 +76,17 @@ bool imx233_is_clock_enable(enum imx233_clock_t clk) | |||
76 | 76 | ||
77 | void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) | 77 | void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) |
78 | { | 78 | { |
79 | /* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */ | ||
79 | switch(clk) | 80 | switch(clk) |
80 | { | 81 | { |
81 | case CLK_PIX: | 82 | case CLK_PIX: |
82 | __REG_CLR(HW_CLKCTRL_PIX) = HW_CLKCTRL_PIX__DIV_BM; | 83 | HW_CLKCTRL_PIX &= ~HW_CLKCTRL_PIX__DIV_BM; |
83 | __REG_SET(HW_CLKCTRL_PIX) = div; | 84 | HW_CLKCTRL_PIX |= div; |
84 | while(HW_CLKCTRL_PIX & __CLK_BUSY); | 85 | while(HW_CLKCTRL_PIX & __CLK_BUSY); |
85 | break; | 86 | break; |
86 | case CLK_SSP: | 87 | case CLK_SSP: |
87 | __REG_CLR(HW_CLKCTRL_SSP) = HW_CLKCTRL_SSP__DIV_BM; | 88 | HW_CLKCTRL_SSP &= ~HW_CLKCTRL_SSP__DIV_BM; |
88 | __REG_SET(HW_CLKCTRL_SSP) = div; | 89 | HW_CLKCTRL_SSP |= div; |
89 | while(HW_CLKCTRL_SSP & __CLK_BUSY); | 90 | while(HW_CLKCTRL_SSP & __CLK_BUSY); |
90 | break; | 91 | break; |
91 | case CLK_CPU: | 92 | case CLK_CPU: |
@@ -94,8 +95,8 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) | |||
94 | while(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__BUSY_REF_CPU); | 95 | while(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__BUSY_REF_CPU); |
95 | break; | 96 | break; |
96 | case CLK_EMI: | 97 | case CLK_EMI: |
97 | __REG_CLR(HW_CLKCTRL_EMI) = HW_CLKCTRL_EMI__DIV_EMI_BM; | 98 | HW_CLKCTRL_EMI &= ~HW_CLKCTRL_EMI__DIV_EMI_BM; |
98 | __REG_SET(HW_CLKCTRL_EMI) = div; | 99 | HW_CLKCTRL_EMI |= div; |
99 | while(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__BUSY_REF_EMI); | 100 | while(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__BUSY_REF_EMI); |
100 | break; | 101 | break; |
101 | case CLK_HBUS: | 102 | case CLK_HBUS: |
@@ -104,8 +105,8 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) | |||
104 | while(HW_CLKCTRL_HBUS & __CLK_BUSY); | 105 | while(HW_CLKCTRL_HBUS & __CLK_BUSY); |
105 | break; | 106 | break; |
106 | case CLK_XBUS: | 107 | case CLK_XBUS: |
107 | __REG_CLR(HW_CLKCTRL_XBUS) = HW_CLKCTRL_XBUS__DIV_BM; | 108 | HW_CLKCTRL_XBUS &= ~HW_CLKCTRL_XBUS__DIV_BM; |
108 | __REG_SET(HW_CLKCTRL_XBUS) = div; | 109 | HW_CLKCTRL_XBUS |= div; |
109 | while(HW_CLKCTRL_XBUS & __CLK_BUSY); | 110 | while(HW_CLKCTRL_XBUS & __CLK_BUSY); |
110 | break; | 111 | break; |
111 | default: return; | 112 | default: return; |
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.h b/firmware/target/arm/imx233/clkctrl-imx233.h index 8a52620f7e..ae2e0465a0 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.h +++ b/firmware/target/arm/imx233/clkctrl-imx233.h | |||
@@ -52,6 +52,7 @@ | |||
52 | #define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16) | 52 | #define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16) |
53 | #define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20) | 53 | #define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20) |
54 | 54 | ||
55 | /* warning: this register doesn't have a CLR/SET variant ! */ | ||
55 | #define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40)) | 56 | #define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40)) |
56 | #define HW_CLKCTRL_XBUS__DIV_BP 0 | 57 | #define HW_CLKCTRL_XBUS__DIV_BP 0 |
57 | #define HW_CLKCTRL_XBUS__DIV_BM 0x3ff | 58 | #define HW_CLKCTRL_XBUS__DIV_BM 0x3ff |
@@ -62,14 +63,17 @@ | |||
62 | #define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28) | 63 | #define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28) |
63 | #define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30) | 64 | #define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30) |
64 | 65 | ||
66 | /* warning: this register doesn't have a CLR/SET variant ! */ | ||
65 | #define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60)) | 67 | #define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60)) |
66 | #define HW_CLKCTRL_PIX__DIV_BP 0 | 68 | #define HW_CLKCTRL_PIX__DIV_BP 0 |
67 | #define HW_CLKCTRL_PIX__DIV_BM 0xfff | 69 | #define HW_CLKCTRL_PIX__DIV_BM 0xfff |
68 | 70 | ||
71 | /* warning: this register doesn't have a CLR/SET variant ! */ | ||
69 | #define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70)) | 72 | #define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70)) |
70 | #define HW_CLKCTRL_SSP__DIV_BP 0 | 73 | #define HW_CLKCTRL_SSP__DIV_BP 0 |
71 | #define HW_CLKCTRL_SSP__DIV_BM 0x1ff | 74 | #define HW_CLKCTRL_SSP__DIV_BM 0x1ff |
72 | 75 | ||
76 | /* warning: this register doesn't have a CLR/SET variant ! */ | ||
73 | #define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0)) | 77 | #define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0)) |
74 | #define HW_CLKCTRL_EMI__DIV_EMI_BP 0 | 78 | #define HW_CLKCTRL_EMI__DIV_EMI_BP 0 |
75 | #define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f | 79 | #define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f |
@@ -94,6 +98,7 @@ | |||
94 | #define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6) | 98 | #define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6) |
95 | #define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7) | 99 | #define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7) |
96 | 100 | ||
101 | /* warning: this register doesn't have a CLR/SET variant ! */ | ||
97 | #define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120)) | 102 | #define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120)) |
98 | #define HW_CLKCTRL_RESET_CHIP 0x2 | 103 | #define HW_CLKCTRL_RESET_CHIP 0x2 |
99 | #define HW_CLKCTRL_RESET_DIG 0x1 | 104 | #define HW_CLKCTRL_RESET_DIG 0x1 |