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authorAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 15:30:46 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 15:30:46 +0200
commite6a931301fe8ef5800b2fd1114f932e9fd9e4db0 (patch)
tree44b86dfad906eaa6fad092af4f0ee6a467f190d4 /firmware/target/arm/imx233/emi-imx233.h
parent2a01b3766f44a14451653e48fd59e9724f0173fb (diff)
downloadrockbox-e6a931301fe8ef5800b2fd1114f932e9fd9e4db0.tar.gz
rockbox-e6a931301fe8ef5800b2fd1114f932e9fd9e4db0.zip
imx233: rewrite emi using new register headers
Change-Id: Ie893162aac38ea3aaf73b4e84e54be714a5fc33f
Diffstat (limited to 'firmware/target/arm/imx233/emi-imx233.h')
-rw-r--r--firmware/target/arm/imx233/emi-imx233.h221
1 files changed, 3 insertions, 218 deletions
diff --git a/firmware/target/arm/imx233/emi-imx233.h b/firmware/target/arm/imx233/emi-imx233.h
index 8106d27dfe..cab2e5e8c0 100644
--- a/firmware/target/arm/imx233/emi-imx233.h
+++ b/firmware/target/arm/imx233/emi-imx233.h
@@ -25,225 +25,10 @@
25#include "system.h" 25#include "system.h"
26#include "system-target.h" 26#include "system-target.h"
27 27
28#define HW_EMI_BASE 0x80020000 28#include "regs/regs-emi.h"
29#include "regs/regs-dram.h"
29 30
30#define HW_EMI_CTRL (*(volatile uint32_t *)(HW_EMI_BASE + 0x0)) 31#define HW_DRAM_CTLxx(xx) (*(&HW_DRAM_CTL00 + (xx)))
31#define HW_EMI_CTRL__DLL_SHIFT_RESET (1 << 25)
32#define HW_EMI_CTRL__DLL_RESET (1 << 24)
33
34/* this register is undocumented but exists, I put the whole doc here */
35#define HW_EMI_STAT (*(volatile uint32_t *)(HW_EMI_BASE + 0x10))
36#define HW_EMI_STAT__DRAM_PRESENT (1 << 31)
37#define HW_EMI_STAT__NOR_PRESENT (1 << 30)
38#define HW_EMI_STAT__LARGE_DRAM_ENABLED (1 << 29)
39#define HW_EMI_STAT__DRAM_HALTED (1 << 1)
40#define HW_EMI_STAT__NOR_BUSY (1 << 0)
41
42/* another undocumented registers (there are some more) */
43#define HW_EMI_TIME (*(volatile uint32_t *)(HW_EMI_BASE + 0x20))
44#define HW_EMI_TIME__THZ_BP 24
45#define HW_EMI_TIME__THZ_BM (0xf << 24)
46#define HW_EMI_TIME__TDH_BP 16
47#define HW_EMI_TIME__TDH_BM (0xf << 16)
48#define HW_EMI_TIME__TDS_BP 8
49#define HW_EMI_TIME__TDS_BM (0x1f << 8)
50#define HW_EMI_TIME__TAS_BP 0
51#define HW_EMI_TIME__TAS_BM (0xf << 0)
52
53/** WARNING: the HW_DRAM_* registers don't have a SCT variant ! */
54#define HW_DRAM_BASE 0x800E0000
55
56#define HW_DRAM_CTLxx(xx) (*(volatile uint32_t *)(HW_DRAM_BASE + 0x4 * (xx)))
57
58#define HW_DRAM_CTL00 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x0))
59#define HW_DRAM_CTL01 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x4))
60#define HW_DRAM_CTL02 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x8))
61#define HW_DRAM_CTL03 (*(volatile uint32_t *)(HW_DRAM_BASE + 0xc))
62
63#define HW_DRAM_CTL04 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x10))
64#define HW_DRAM_CTL04__DLL_BYPASS_MODE (1 << 24)
65#define HW_DRAM_CTL04__DLLLOCKREG (1 << 16)
66
67#define HW_DRAM_CTL05 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x14))
68#define HW_DRAM_CTL05__EN_LOWPOWER_MODE (1 << 0)
69
70#define HW_DRAM_CTL06 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x18))
71#define HW_DRAM_CTL07 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x1c))
72
73#define HW_DRAM_CTL08 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x20))
74#define HW_DRAM_CTL08__SREFRESH (1 << 8)
75
76#define HW_DRAM_CTL09 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x24))
77
78#define HW_DRAM_CTL10 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x28))
79#define HW_DRAM_CTL10__TEMRS_BP 8
80#define HW_DRAM_CTL10__TEMRS_BM (0x3 << 8)
81
82#define HW_DRAM_CTL11 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x2c))
83#define HW_DRAM_CTL11__CASLAT_BP 0
84#define HW_DRAM_CTL11__CASLAT_BM (0x7 << 0)
85
86#define HW_DRAM_CTL12 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x30))
87#define HW_DRAM_CTL12__TCKE_BP 0
88#define HW_DRAM_CTL12__TCKE_BM (0x7 << 0)
89#define HW_DRAM_CTL12__TRRD_BP 16
90#define HW_DRAM_CTL12__TRRD_BM (0x7 << 16)
91#define HW_DRAM_CTL12__TWR_INT_BP 24
92#define HW_DRAM_CTL12__TWR_INT_BM (0x7 << 24)
93
94#define HW_DRAM_CTL13 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x34))
95#define HW_DRAM_CTL13__TWTR_BP 0
96#define HW_DRAM_CTL13__TWTR_BM (0x7 << 0)
97#define HW_DRAM_CTL13__CASLAT_LIN_BP 16
98#define HW_DRAM_CTL13__CASLAT_LIN_BM (0xf << 16)
99#define HW_DRAM_CTL13__CASLAT_LIN_GATE_BP 24
100#define HW_DRAM_CTL13__CASLAT_LIN_GATE_BM (0xf << 24)
101
102#define HW_DRAM_CTL14 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x38))
103
104#define HW_DRAM_CTL15 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x3c))
105#define HW_DRAM_CTL15__TDAL_BP 16
106#define HW_DRAM_CTL15__TDAL_BM (0xf << 16)
107#define HW_DRAM_CTL15__TRP_BP 24
108#define HW_DRAM_CTL15__TRP_BM (0xf << 24)
109
110#define HW_DRAM_CTL16 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x40))
111#define HW_DRAM_CTL16__TMRD_BP 24
112#define HW_DRAM_CTL16__TMRD_BM (0x1f << 24)
113
114#define HW_DRAM_CTL17 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x44))
115#define HW_DRAM_CTL17__TRC_BP 0
116#define HW_DRAM_CTL17__TRC_BM (0x1f << 0)
117#define HW_DRAM_CTL17__DLL_INCREMENT_BP 8
118#define HW_DRAM_CTL17__DLL_INCREMENT_BM (0xff << 0)
119#define HW_DRAM_CTL17__DLL_START_POINT_BP 24
120#define HW_DRAM_CTL17__DLL_START_POINT_BM (0xff << 24)
121
122#define HW_DRAM_CTL18 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x48))
123#define HW_DRAM_CTL17__DLL_DQS_DELAY_0_BP 16
124#define HW_DRAM_CTL17__DLL_DQS_DELAY_0_BM (0x7f << 16)
125#define HW_DRAM_CTL17__DLL_DQS_DELAY_1_BP 24
126#define HW_DRAM_CTL17__DLL_DQS_DELAY_1_BM (0x7f << 24)
127
128#define HW_DRAM_CTL19 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x4c))
129#define HW_DRAM_CTL19__DQS_OUT_SHIFT_BP 16
130#define HW_DRAM_CTL19__DQS_OUT_SHIFT_BM (0x7f << 16)
131
132#define HW_DRAM_CTL20 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x50))
133#define HW_DRAM_CTL20__WR_DQS_SHIFT_BP 0
134#define HW_DRAM_CTL20__WR_DQS_SHIFT_BM (0x7f << 0)
135#define HW_DRAM_CTL20__TRAS_MIN_BP 16
136#define HW_DRAM_CTL20__TRAS_MIN_BM (0xff << 16)
137#define HW_DRAM_CTL20__TRCD_INT_BP 24
138#define HW_DRAM_CTL20__TRCD_INT_BM (0xff << 24)
139
140#define HW_DRAM_CTL21 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x54))
141#define HW_DRAM_CTL21__TRFC_BP 0
142#define HW_DRAM_CTL21__TRFC_BM (0xff << 0)
143
144#define HW_DRAM_CTL22 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x58))
145#define HW_DRAM_CTL23 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x5c))
146#define HW_DRAM_CTL24 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x60))
147#define HW_DRAM_CTL25 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x64))
148
149#define HW_DRAM_CTL26 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x68))
150#define HW_DRAM_CTL26__TREF_BP 0
151#define HW_DRAM_CTL26__TREF_BM (0xfff << 0)
152
153#define HW_DRAM_CTL27 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x6c))
154#define HW_DRAM_CTL28 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x70))
155#define HW_DRAM_CTL29 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x74))
156#define HW_DRAM_CTL30 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x78))
157
158#define HW_DRAM_CTL31 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x7c))
159#define HW_DRAM_CTL31__TDLL_BP 16
160#define HW_DRAM_CTL31__TDLL_BM (0xffff << 16)
161
162#define HW_DRAM_CTL32 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x80))
163#define HW_DRAM_CTL32__TRAS_MAX_BP 0
164#define HW_DRAM_CTL32__TRAS_MAX_BM (0xffff << 0)
165#define HW_DRAM_CTL32__TXSNR_BP 16
166#define HW_DRAM_CTL32__TXSNR_BM (0xffff << 16)
167
168#define HW_DRAM_CTL33 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x84))
169#define HW_DRAM_CTL33__TXSR_BP 0
170#define HW_DRAM_CTL33__TXSR_BM (0xffff << 0)
171
172#define HW_DRAM_CTL34 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x88))
173#define HW_DRAM_CTL34__TINIT_BP 0
174#define HW_DRAM_CTL34__TINIT_BM 0xffffff
175
176#define HW_DRAM_CTL35 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x8c))
177#define HW_DRAM_CTL36 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x90))
178#define HW_DRAM_CTL37 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x94))
179#define HW_DRAM_CTL38 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x98))
180#define HW_DRAM_CTL39 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x9a))
181
182#define HW_DRAM_CTL40 (*(volatile uint32_t *)(HW_DRAM_BASE + 0xa0))
183#define HW_DRAM_CTL40__TPDEX_BP 16
184#define HW_DRAM_CTL40__TPDEX_BM (0xffff << 16)
185
186/** Interesting fields:
187 * - TCKE: CTL12
188 * - TDAL: CTL15
189 * - TDLL: CTL31
190 * - TEMRS: CTL10
191 * - TINIT: CTL34
192 * - TMRD: CTL16
193 * - TPDEX: CTL40
194 * - TRAS_MAX: CTL32
195 * - TRAS_MIN: CTL20
196 * - TRC: CTL17
197 * - TRCD_INT: CTL20
198 * - TREF: CTL26
199 * - TRFC: CTL21
200 * - TRP: CTL15
201 * - TRRD: CTL12
202 * - TWR_INT: CTL12
203 * - TWTR: CTL13
204 * - TXSNR: CTL32
205 * - TXSR: CTL33
206 * - DLL_DQS_DELAY_BYPASS_0
207 * - DLL_DQS_DELAY_BYPASS_1
208 * - DQS_OUT_SHIFT_BYPASS
209 * - WR_DQS_SHIFT_BYPASS
210 * - DLL_INCREMENT: CTL17
211 * - DLL_START_POINT: CTL17
212 * - DLL_DQS_DELAY_0: CTL18
213 * - DLL_DQS_DELAY_1: CTL18
214 * - DQS_OUT_SHIFT: CTL19
215 * - WR_DQS_SHIFT: CTL20
216 * - CAS: CTL11
217 * - DLL_BYPASS_MODE: CTL04
218 * - SREFRESH: CTL08
219 * - CASLAT_LIN: CTL13
220 * - CASLAT_LIN_GATE: CTL13
221 *
222 * Interesting registers:
223 * - CTL04: DLL_BYPASS_MODE
224 * - CTL08: SREFRESH
225 * - CTL10: TEMRS
226 * - CTL11: CASLAT
227 * - CTL12: TCKE TRRD TWR_INT
228 * - CTL13: TWTR CASLAT_LIN CASLAT_LIN_GATE
229 * - CTL15: TDAL TRP
230 * - CTL16: TMRD
231 * - CTL17: TRC DLL_INCREMENT DLL_START_POINT
232 * - CTL18: DLL_DQS_DELAY_0 DLL_DQS_DELAY_1
233 * - CTL19: DQS_OUT_SHIFT
234 * - CTL20: WR_DQS_SHIFT TRAS_MIN TRCD_INT
235 * - CTL21 TRFC
236 * - CTL26: TREF
237 * - CTL31: TDLL
238 * - CTL32: TRAS_MAX TXSNR TXSR: CTL33
239 * - CTL34: TINIT
240 * - CTL40: TPDEX
241
242 * - DLL_DQS_DELAY_BYPASS_0
243 * - DLL_DQS_DELAY_BYPASS_1
244 * - DQS_OUT_SHIFT_BYPASS
245 * - WR_DQS_SHIFT_BYPASS
246 */
247 32
248/** 33/**
249 * Absolute maximum EMI speed: 151.58 MHz (mDDR), 130.91 MHz (DDR) 34 * Absolute maximum EMI speed: 151.58 MHz (mDDR), 130.91 MHz (DDR)
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-27 11:16:16 +0000