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author | Michael Sevakis <jethead71@rockbox.org> | 2007-07-05 07:14:24 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2007-07-05 07:14:24 +0000 |
commit | 60efd38bbea318292502c398d41ba3c1044bbb0c (patch) | |
tree | 3ceab1cda84743906e601f2074a50054097a5a4c /firmware/export | |
parent | 21b90e3466b28b9885887f679b264ba4073b76bc (diff) | |
download | rockbox-60efd38bbea318292502c398d41ba3c1044bbb0c.tar.gz rockbox-60efd38bbea318292502c398d41ba3c1044bbb0c.zip |
Gigabeat: Use vectored IRQ mode interrupts and add a trap for unhandled ones.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13792 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/s3c2440.h | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/firmware/export/s3c2440.h b/firmware/export/s3c2440.h index 4a799da3e2..72c33e227c 100644 --- a/firmware/export/s3c2440.h +++ b/firmware/export/s3c2440.h | |||
@@ -16,6 +16,8 @@ | |||
16 | * KIND, either express or implied. | 16 | * KIND, either express or implied. |
17 | * | 17 | * |
18 | ****************************************************************************/ | 18 | ****************************************************************************/ |
19 | #ifndef __S3C2440_H__ | ||
20 | #define __S3C2440_H__ | ||
19 | 21 | ||
20 | /* Memory Controllers */ | 22 | /* Memory Controllers */ |
21 | 23 | ||
@@ -74,6 +76,86 @@ | |||
74 | #define SUBSRCPND (*(volatile int *)0x4A000018) /* Sub source pending */ | 76 | #define SUBSRCPND (*(volatile int *)0x4A000018) /* Sub source pending */ |
75 | #define INTSUBMSK (*(volatile int *)0x4A00001C) /* Interrupt sub mask */ | 77 | #define INTSUBMSK (*(volatile int *)0x4A00001C) /* Interrupt sub mask */ |
76 | 78 | ||
79 | /* Interrupt indexes - INTOFFSET - IRQ mode only */ | ||
80 | /* Arbiter 5 => Arbiter 6 Req 5 */ | ||
81 | #define ADC_OFFSET 31 /* REQ4 */ | ||
82 | #define RTC_OFFSET 30 /* REQ3 */ | ||
83 | #define SPI1_OFFSET 29 /* REQ2 */ | ||
84 | #define UART0_OFFSET 28 /* REQ1 */ | ||
85 | /* Arbiter 4 => Arbiter 6 Req 4 */ | ||
86 | #define IIC_OFFSET 27 /* REQ5 */ | ||
87 | #define USBH_OFFSET 26 /* REQ4 */ | ||
88 | #define USBD_OFFSET 25 /* REQ3 */ | ||
89 | #define NFCON_OFFSET 24 /* REQ2 */ | ||
90 | #define UART1_OFFSET 23 /* REQ1 */ | ||
91 | #define SPI0_OFFSET 22 /* REQ0 */ | ||
92 | /* Arbiter 3 => Arbiter 6 Req 3 */ | ||
93 | #define SDI_OFFSET 21 /* REQ5 */ | ||
94 | #define DMA3_OFFSET 20 /* REQ4 */ | ||
95 | #define DMA2_OFFSET 19 /* REQ3 */ | ||
96 | #define DMA1_OFFSET 18 /* REQ2 */ | ||
97 | #define DMA0_OFFSET 17 /* REQ1 */ | ||
98 | #define LCD_OFFSET 16 /* REQ0 */ | ||
99 | /* Arbiter 2 => Arbiter 6 Req 2 */ | ||
100 | #define UART2_OFFSET 15 /* REQ5 */ | ||
101 | #define TIMER4_OFFSET 14 /* REQ4 */ | ||
102 | #define TIMER3_OFFSET 13 /* REQ3 */ | ||
103 | #define TIMER2_OFFSET 12 /* REQ2 */ | ||
104 | #define TIMER1_OFFSET 11 /* REQ1 */ | ||
105 | #define TIMER0_OFFSET 10 /* REQ0 */ | ||
106 | /* Arbiter 1 => Arbiter 6 Req 1 */ | ||
107 | #define WDT_AC97_OFFSET 9 /* REQ5 */ | ||
108 | #define TICK_OFFSET 8 /* REQ4 */ | ||
109 | #define nBATT_FLT_OFFSET 7 /* REQ3 */ | ||
110 | #define CAM_OFFSET 6 /* REQ2 */ | ||
111 | #define EINT8_23_OFFSET 5 /* REQ1 */ | ||
112 | #define EINT4_7_OFFSET 4 /* REQ0 */ | ||
113 | /* Arbiter 0 => Arbiter 6 Req 0 */ | ||
114 | #define EINT3_OFFSET 3 /* REQ4 */ | ||
115 | #define EINT2_OFFSET 2 /* REQ3 */ | ||
116 | #define EINT1_OFFSET 1 /* REQ2 */ | ||
117 | #define EINT0_OFFSET 0 /* REQ1 */ | ||
118 | |||
119 | /* Interrupt bitmasks - SRCPND, INTMOD, INTMSK, INTPND */ | ||
120 | /* Arbiter 5 => Arbiter 6 Req 5 */ | ||
121 | #define ADC_MASK (1 << 31) /* REQ4 */ | ||
122 | #define RTC_MASK (1 << 30) /* REQ3 */ | ||
123 | #define SPI1_MASK (1 << 29) /* REQ2 */ | ||
124 | #define UART0_MASK (1 << 28) /* REQ1 */ | ||
125 | /* Arbiter 4 => Arbiter 6 Req 4 */ | ||
126 | #define IIC_MASK (1 << 27) /* REQ5 */ | ||
127 | #define USBH_MASK (1 << 26) /* REQ4 */ | ||
128 | #define USBD_MASK (1 << 25) /* REQ3 */ | ||
129 | #define NFCON_MASK (1 << 24) /* REQ2 */ | ||
130 | #define UART1_MASK (1 << 23) /* REQ1 */ | ||
131 | #define SPI0_MASK (1 << 22) /* REQ0 */ | ||
132 | /* Arbiter 3 => Arbiter 6 Req 3 */ | ||
133 | #define SDI_MASK (1 << 21) /* REQ5 */ | ||
134 | #define DMA3_MASK (1 << 20) /* REQ4 */ | ||
135 | #define DMA2_MASK (1 << 19) /* REQ3 */ | ||
136 | #define DMA1_MASK (1 << 18) /* REQ2 */ | ||
137 | #define DMA0_MASK (1 << 17) /* REQ1 */ | ||
138 | #define LCD_MASK (1 << 16) /* REQ0 */ | ||
139 | /* Arbiter 2 => Arbiter 6 Req 2 */ | ||
140 | #define UART2_MASK (1 << 15) /* REQ5 */ | ||
141 | #define TIMER4_MASK (1 << 14) /* REQ4 */ | ||
142 | #define TIMER3_MASK (1 << 13) /* REQ3 */ | ||
143 | #define TIMER2_MASK (1 << 12) /* REQ2 */ | ||
144 | #define TIMER1_MASK (1 << 11) /* REQ1 */ | ||
145 | #define TIMER0_MASK (1 << 10) /* REQ0 */ | ||
146 | /* Arbiter 1 => Arbiter 6 Req 1 */ | ||
147 | #define WDT_AC97_MASK (1 << 9) /* REQ5 */ | ||
148 | #define TICK_MASK (1 << 8) /* REQ4 */ | ||
149 | #define nBATT_FLT_MASK (1 << 7) /* REQ3 */ | ||
150 | #define CAM_MASK (1 << 6) /* REQ2 */ | ||
151 | #define EINT8_23_MASK (1 << 5) /* REQ1 */ | ||
152 | #define EINT4_7_MASK (1 << 4) /* REQ0 */ | ||
153 | /* Arbiter 0 => Arbiter 6 Req 0 */ | ||
154 | #define EINT3_MASK (1 << 3) /* REQ4 */ | ||
155 | #define EINT2_MASK (1 << 2) /* REQ3 */ | ||
156 | #define EINT1_MASK (1 << 1) /* REQ2 */ | ||
157 | #define EINT0_MASK (1 << 0) /* REQ1 */ | ||
158 | |||
77 | /* DMA */ | 159 | /* DMA */ |
78 | 160 | ||
79 | #define DISRC0 (*(volatile int *)0x4B000000) /* DMA 0 initial source */ | 161 | #define DISRC0 (*(volatile int *)0x4B000000) /* DMA 0 initial source */ |
@@ -465,3 +547,4 @@ | |||
465 | #define DRAM1 0x31000000 | 547 | #define DRAM1 0x31000000 |
466 | #define BOOTRAM 0x40000000 | 548 | #define BOOTRAM 0x40000000 |
467 | 549 | ||
550 | #endif /* __S3C2440_H__ */ | ||