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| author | Michael Sparmann <theseven@rockbox.org> | 2009-10-05 16:01:26 +0000 |
|---|---|---|
| committer | Michael Sparmann <theseven@rockbox.org> | 2009-10-05 16:01:26 +0000 |
| commit | 271c67e802c65b243c7e4c76e276a893345f15fe (patch) | |
| tree | 10e1389be74cfc62c0651a590c4496fb2e1fea34 /firmware/export | |
| parent | 79bf2da1ef6f8f16c44ba8fa6d71ea6870a19767 (diff) | |
| download | rockbox-271c67e802c65b243c7e4c76e276a893345f15fe.tar.gz rockbox-271c67e802c65b243c7e4c76e276a893345f15fe.zip | |
Fix the user timer on iPod Nano 2G
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22959 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
| -rw-r--r-- | firmware/export/s5l8700.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index 801e8a0857..f652a62a2e 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
| @@ -126,10 +126,16 @@ | |||
| 126 | #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ | 126 | #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ |
| 127 | #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ | 127 | #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ |
| 128 | #if CONFIG_CPU==S5L8701 | 128 | #if CONFIG_CPU==S5L8701 |
| 129 | #define INTMSK_TIMERA (1<<5) | ||
| 129 | #define INTMSK_TIMERB (1<<5) | 130 | #define INTMSK_TIMERB (1<<5) |
| 131 | #define INTMSK_TIMERC (1<<5) | ||
| 132 | #define INTMSK_TIMERD (1<<5) | ||
| 130 | #define INTMSK_ECC (1<<19) | 133 | #define INTMSK_ECC (1<<19) |
| 131 | #else | 134 | #else |
| 135 | #define INTMSK_TIMERA (1<<5) | ||
| 132 | #define INTMSK_TIMERB (1<<7) | 136 | #define INTMSK_TIMERB (1<<7) |
| 137 | #define INTMSK_TIMERC (1<<8) | ||
| 138 | #define INTMSK_TIMERD (1<<9) | ||
| 133 | #endif | 139 | #endif |
| 134 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ | 140 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ |
| 135 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ | 141 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ |