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author | Jens Arnold <amiconn@rockbox.org> | 2006-05-07 20:20:27 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2006-05-07 20:20:27 +0000 |
commit | 61b8604a9cd46af54282731b2833f7f22d8a7e18 (patch) | |
tree | 9d3eaafc0995ccd718d3dbe1b4a82bf672c9b608 /firmware/drivers/ata_mmc.c | |
parent | 595a2040204a5f2de2ca3249e215de25983d6711 (diff) | |
download | rockbox-61b8604a9cd46af54282731b2833f7f22d8a7e18.tar.gz rockbox-61b8604a9cd46af54282731b2833f7f22d8a7e18.zip |
Ondio: (Hopefully) fix the occasional freezes during playback: Use DMA channel 0 for MMC transfer. As it has higher priority than channel 3 (used for playback), the risk of serial receive overruns is minimised.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9885 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/drivers/ata_mmc.c')
-rw-r--r-- | firmware/drivers/ata_mmc.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/firmware/drivers/ata_mmc.c b/firmware/drivers/ata_mmc.c index f398846387..b2e79c419a 100644 --- a/firmware/drivers/ata_mmc.c +++ b/firmware/drivers/ata_mmc.c | |||
@@ -583,12 +583,12 @@ static int receive_block(unsigned char *inbuf, int size, long timeout) | |||
583 | SCR1 = 0; /* disable serial */ | 583 | SCR1 = 0; /* disable serial */ |
584 | SSR1 = 0; /* clear all flags */ | 584 | SSR1 = 0; /* clear all flags */ |
585 | 585 | ||
586 | /* setup DMA channel 2 */ | 586 | /* setup DMA channel 0 */ |
587 | CHCR2 = 0; /* disable */ | 587 | CHCR0 = 0; /* disable */ |
588 | SAR2 = RDR1_ADDR; | 588 | SAR0 = RDR1_ADDR; |
589 | DAR2 = (unsigned long) inbuf; | 589 | DAR0 = (unsigned long) inbuf; |
590 | DTCR2 = size; | 590 | DTCR0 = size; |
591 | CHCR2 = 0x4601; /* fixed source address, RXI1, enable */ | 591 | CHCR0 = 0x4601; /* fixed source address, RXI1, enable */ |
592 | DMAOR = 0x0001; | 592 | DMAOR = 0x0001; |
593 | SCR1 = (SCI_RE|SCI_RIE); /* kick off DMA */ | 593 | SCR1 = (SCI_RE|SCI_RIE); /* kick off DMA */ |
594 | 594 | ||
@@ -600,7 +600,7 @@ static int receive_block(unsigned char *inbuf, int size, long timeout) | |||
600 | bg_copy_swap(); | 600 | bg_copy_swap(); |
601 | yield(); /* be nice */ | 601 | yield(); /* be nice */ |
602 | 602 | ||
603 | while (!(CHCR2 & 0x0002)); /* wait for end of DMA */ | 603 | while (!(CHCR0 & 0x0002)); /* wait for end of DMA */ |
604 | while (!(SSR1 & SCI_ORER)); /* wait for the trailing bytes */ | 604 | while (!(SSR1 & SCI_ORER)); /* wait for the trailing bytes */ |
605 | SCR1 = 0; | 605 | SCR1 = 0; |
606 | serial_mode = SER_DISABLED; | 606 | serial_mode = SER_DISABLED; |
@@ -625,19 +625,19 @@ static int send_block(int size, unsigned char start_token, long timeout) | |||
625 | SCR1 = 0; /* disable serial */ | 625 | SCR1 = 0; /* disable serial */ |
626 | SSR1 = 0; /* clear all flags */ | 626 | SSR1 = 0; /* clear all flags */ |
627 | 627 | ||
628 | /* setup DMA channel 2 */ | 628 | /* setup DMA channel 0 */ |
629 | CHCR2 = 0; /* disable */ | 629 | CHCR0 = 0; /* disable */ |
630 | SAR2 = (unsigned long)(curbuf + 1); | 630 | SAR0 = (unsigned long)(curbuf + 1); |
631 | DAR2 = TDR1_ADDR; | 631 | DAR0 = TDR1_ADDR; |
632 | DTCR2 = size + 3; /* start token + block + dummy crc */ | 632 | DTCR0 = size + 3; /* start token + block + dummy crc */ |
633 | CHCR2 = 0x1701; /* fixed dest. address, TXI1, enable */ | 633 | CHCR0 = 0x1701; /* fixed dest. address, TXI1, enable */ |
634 | DMAOR = 0x0001; | 634 | DMAOR = 0x0001; |
635 | SCR1 = (SCI_TE|SCI_TIE); /* kick off DMA */ | 635 | SCR1 = (SCI_TE|SCI_TIE); /* kick off DMA */ |
636 | 636 | ||
637 | bg_copy_swap(); | 637 | bg_copy_swap(); |
638 | yield(); /* be nice */ | 638 | yield(); /* be nice */ |
639 | 639 | ||
640 | while (!(CHCR2 & 0x0002)); /* wait for end of DMA */ | 640 | while (!(CHCR0 & 0x0002)); /* wait for end of DMA */ |
641 | while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */ | 641 | while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */ |
642 | SCR1 = 0; | 642 | SCR1 = 0; |
643 | serial_mode = SER_DISABLED; | 643 | serial_mode = SER_DISABLED; |