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author | Rafaël Carré <rafael.carre@gmail.com> | 2010-06-11 05:15:17 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-06-11 05:15:17 +0000 |
commit | e3263b70c36a955b2b86b985092af0a39306a6ff (patch) | |
tree | 73e8ed38bbe370d2bc2669f819916d9814001b4d /apps | |
parent | 95ef367854f03760ea248ad62900162efe5b98c9 (diff) | |
download | rockbox-e3263b70c36a955b2b86b985092af0a39306a6ff.tar.gz rockbox-e3263b70c36a955b2b86b985092af0a39306a6ff.zip |
CPP substitution isn't made inside " ", but we need " " when using , in a gas macro argument
Modify HIGH_REGS macro to store/load only one range of registers
When the range isn't contigous (in MC_put_x_8*), shift registers to make
it contigous (r4 and r5 are now unused by these functions)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26759 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'apps')
-rw-r--r-- | apps/plugins/mpegplayer/motion_comp_arm_s.S | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/apps/plugins/mpegplayer/motion_comp_arm_s.S b/apps/plugins/mpegplayer/motion_comp_arm_s.S index 49628c6ad5..1ec1b0686e 100644 --- a/apps/plugins/mpegplayer/motion_comp_arm_s.S +++ b/apps/plugins/mpegplayer/motion_comp_arm_s.S | |||
@@ -183,9 +183,9 @@ MC_put_o_8_align3: | |||
183 | .endm | 183 | .endm |
184 | 184 | ||
185 | #if ARM_ARCH >= 6 | 185 | #if ARM_ARCH >= 6 |
186 | #define HIGH_REGS r9 | 186 | #define HIGHEST_REG r9 |
187 | #else | 187 | #else |
188 | #define HIGH_REGS r9-r11 | 188 | #define HIGHEST_REG r11 |
189 | #endif | 189 | #endif |
190 | 190 | ||
191 | .align | 191 | .align |
@@ -193,7 +193,7 @@ MC_put_o_8_align3: | |||
193 | MC_put_x_16: | 193 | MC_put_x_16: |
194 | @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height) | 194 | @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height) |
195 | @@ pld [r1] | 195 | @@ pld [r1] |
196 | stmfd sp!, {r4-r8, HIGH_REGS, lr} @ R14 is also called LR | 196 | stmfd sp!, {r4-HIGHEST_REG, lr} @ R14 is also called LR |
197 | and r4, r1, #3 | 197 | and r4, r1, #3 |
198 | ldr r12, 2f | 198 | ldr r12, 2f |
199 | #if ARM_ARCH < 6 | 199 | #if ARM_ARCH < 6 |
@@ -218,7 +218,7 @@ MC_put_x_16_align0: | |||
218 | subs r3, r3, #1 | 218 | subs r3, r3, #1 |
219 | add r0, r0, r2 | 219 | add r0, r0, r2 |
220 | bne MC_put_x_16_align0 | 220 | bne MC_put_x_16_align0 |
221 | ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. | 221 | ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content. |
222 | 222 | ||
223 | MC_put_x_16_align1: | 223 | MC_put_x_16_align1: |
224 | and r1, r1, #0xFFFFFFFC | 224 | and r1, r1, #0xFFFFFFFC |
@@ -234,7 +234,7 @@ MC_put_x_16_align1: | |||
234 | subs r3, r3, #1 | 234 | subs r3, r3, #1 |
235 | add r0, r0, r2 | 235 | add r0, r0, r2 |
236 | bne 1b | 236 | bne 1b |
237 | ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. | 237 | ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content. |
238 | 238 | ||
239 | MC_put_x_16_align2: | 239 | MC_put_x_16_align2: |
240 | and r1, r1, #0xFFFFFFFC | 240 | and r1, r1, #0xFFFFFFFC |
@@ -250,7 +250,7 @@ MC_put_x_16_align2: | |||
250 | subs r3, r3, #1 | 250 | subs r3, r3, #1 |
251 | add r0, r0, r2 | 251 | add r0, r0, r2 |
252 | bne 1b | 252 | bne 1b |
253 | ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. | 253 | ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content. |
254 | 254 | ||
255 | MC_put_x_16_align3: | 255 | MC_put_x_16_align3: |
256 | and r1, r1, #0xFFFFFFFC | 256 | and r1, r1, #0xFFFFFFFC |
@@ -266,7 +266,7 @@ MC_put_x_16_align3: | |||
266 | subs r3, r3, #1 | 266 | subs r3, r3, #1 |
267 | add r0, r0, r2 | 267 | add r0, r0, r2 |
268 | bne 1b | 268 | bne 1b |
269 | ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. | 269 | ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content. |
270 | 270 | ||
271 | @ ---------------------------------------------------------------- | 271 | @ ---------------------------------------------------------------- |
272 | .align | 272 | .align |
@@ -274,13 +274,13 @@ MC_put_x_16_align3: | |||
274 | MC_put_x_8: | 274 | MC_put_x_8: |
275 | @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height) | 275 | @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height) |
276 | @@ pld [r1] | 276 | @@ pld [r1] |
277 | stmfd sp!, {r4-r6, HIGH_REGS, lr} @ R14 is also called LR | 277 | stmfd sp!, {r6-HIGHEST_REG, lr} @ R14 is also called LR |
278 | and r4, r1, #3 | 278 | and r6, r1, #3 |
279 | ldr r12, 2f | 279 | ldr r12, 2f |
280 | #if ARM_ARCH < 6 | 280 | #if ARM_ARCH < 6 |
281 | mvn r11, r12 | 281 | mvn r11, r12 |
282 | #endif | 282 | #endif |
283 | ldr pc, [pc, r4, lsl #2] | 283 | ldr pc, [pc, r6, lsl #2] |
284 | 2: .word 0x01010101 | 284 | 2: .word 0x01010101 |
285 | .word MC_put_x_8_align0 | 285 | .word MC_put_x_8_align0 |
286 | .word MC_put_x_8_align1 | 286 | .word MC_put_x_8_align1 |
@@ -288,55 +288,55 @@ MC_put_x_8: | |||
288 | .word MC_put_x_8_align3 | 288 | .word MC_put_x_8_align3 |
289 | 289 | ||
290 | MC_put_x_8_align0: | 290 | MC_put_x_8_align0: |
291 | ldmia r1, {r4-r6} | 291 | ldmia r1, {r6-r8} |
292 | add r1, r1, r2 | 292 | add r1, r1, r2 |
293 | @@ pld [r1] | 293 | @@ pld [r1] |
294 | AVG_PW r5, r6 | 294 | AVG_PW r7, r8 |
295 | AVG_PW r4, r5 | 295 | AVG_PW r6, r7 |
296 | stmia r0, {r5-r6} | 296 | stmia r0, {r7-r8} |
297 | subs r3, r3, #1 | 297 | subs r3, r3, #1 |
298 | add r0, r0, r2 | 298 | add r0, r0, r2 |
299 | bne MC_put_x_8_align0 | 299 | bne MC_put_x_8_align0 |
300 | ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. | 300 | ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content. |
301 | 301 | ||
302 | MC_put_x_8_align1: | 302 | MC_put_x_8_align1: |
303 | and r1, r1, #0xFFFFFFFC | 303 | and r1, r1, #0xFFFFFFFC |
304 | 1: ldmia r1, {r4-r6} | 304 | 1: ldmia r1, {r6-r8} |
305 | add r1, r1, r2 | 305 | add r1, r1, r2 |
306 | @@ pld [r1] | 306 | @@ pld [r1] |
307 | ADJ_ALIGN_DW 8, r4, r5, r6 | 307 | ADJ_ALIGN_DW 8, r6, r7, r8 |
308 | AVG_PW r5, r6 | 308 | AVG_PW r7, r8 |
309 | AVG_PW r4, r5 | 309 | AVG_PW r6, r7 |
310 | stmia r0, {r5-r6} | 310 | stmia r0, {r7-r8} |
311 | subs r3, r3, #1 | 311 | subs r3, r3, #1 |
312 | add r0, r0, r2 | 312 | add r0, r0, r2 |
313 | bne 1b | 313 | bne 1b |
314 | ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. | 314 | ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content. |
315 | 315 | ||
316 | MC_put_x_8_align2: | 316 | MC_put_x_8_align2: |
317 | and r1, r1, #0xFFFFFFFC | 317 | and r1, r1, #0xFFFFFFFC |
318 | 1: ldmia r1, {r4-r6} | 318 | 1: ldmia r1, {r6-r8} |
319 | add r1, r1, r2 | 319 | add r1, r1, r2 |
320 | @@ pld [r1] | 320 | @@ pld [r1] |
321 | ADJ_ALIGN_DW 16, r4, r5, r6 | 321 | ADJ_ALIGN_DW 16, r6, r7, r8 |
322 | AVG_PW r5, r6 | 322 | AVG_PW r7, r8 |
323 | AVG_PW r4, r5 | 323 | AVG_PW r6, r7 |
324 | stmia r0, {r5-r6} | 324 | stmia r0, {r7-r8} |
325 | subs r3, r3, #1 | 325 | subs r3, r3, #1 |
326 | add r0, r0, r2 | 326 | add r0, r0, r2 |
327 | bne 1b | 327 | bne 1b |
328 | ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. | 328 | ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content. |
329 | 329 | ||
330 | MC_put_x_8_align3: | 330 | MC_put_x_8_align3: |
331 | and r1, r1, #0xFFFFFFFC | 331 | and r1, r1, #0xFFFFFFFC |
332 | 1: ldmia r1, {r4-r6} | 332 | 1: ldmia r1, {r6-r8} |
333 | add r1, r1, r2 | 333 | add r1, r1, r2 |
334 | @@ pld [r1] | 334 | @@ pld [r1] |
335 | ADJ_ALIGN_DW 24, r4, r5, r6 | 335 | ADJ_ALIGN_DW 24, r6, r7, r8 |
336 | AVG_PW r5, r6 | 336 | AVG_PW r7, r8 |
337 | AVG_PW r4, r5 | 337 | AVG_PW r6, r7 |
338 | stmia r0, {r5-r6} | 338 | stmia r0, {r7-r8} |
339 | subs r3, r3, #1 | 339 | subs r3, r3, #1 |
340 | add r0, r0, r2 | 340 | add r0, r0, r2 |
341 | bne 1b | 341 | bne 1b |
342 | ldmpc regs="r4-r6, HIGH_REGS @@ update PC with LR content. | 342 | ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content. |