CPP substitution isn't made inside " ", but we need " " when using , in a gas macro argument

Modify HIGH_REGS macro to store/load only one range of registers
When the range isn't contigous (in MC_put_x_8*), shift registers to make
it contigous (r4 and r5 are now unused by these functions)

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26759 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 33 insertions, 33 deletions

diff --git a/apps/plugins/mpegplayer/motion_comp_arm_s.S b/apps/plugins/mpegplayer/motion_comp_arm_s.S
index 49628c6ad5..1ec1b0686e 100644
--- a/apps/plugins/mpegplayer/motion_comp_arm_s.S
+++ b/apps/plugins/mpegplayer/motion_comp_arm_s.S
@@ -183,9 +183,9 @@ MC_put_o_8_align3:
 .endm
 
 #if ARM_ARCH >= 6
-#define HIGH_REGS r9
+#define HIGHEST_REG r9
 #else
-#define HIGH_REGS r9-r11
+#define HIGHEST_REG r11
 #endif
 
         .align
@@ -193,7 +193,7 @@ MC_put_o_8_align3:
 MC_put_x_16:
         @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
         @@ pld [r1]
-        stmfd sp!, {r4-r8, HIGH_REGS, lr} @ R14 is also called LR
+        stmfd sp!, {r4-HIGHEST_REG, lr} @ R14 is also called LR
         and r4, r1, #3
         ldr r12, 2f
 #if ARM_ARCH < 6
@@ -218,7 +218,7 @@ MC_put_x_16_align0:
         subs r3, r3, #1
         add r0, r0, r2
         bne MC_put_x_16_align0
-        ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content.
+        ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
 
 MC_put_x_16_align1:
         and r1, r1, #0xFFFFFFFC
@@ -234,7 +234,7 @@ MC_put_x_16_align1:
         subs r3, r3, #1
         add r0, r0, r2
         bne 1b
-        ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content.
+        ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
 
 MC_put_x_16_align2:
         and r1, r1, #0xFFFFFFFC
@@ -250,7 +250,7 @@ MC_put_x_16_align2:
         subs r3, r3, #1
         add r0, r0, r2
         bne 1b
-        ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content.
+        ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
 
 MC_put_x_16_align3:
         and r1, r1, #0xFFFFFFFC
@@ -266,7 +266,7 @@ MC_put_x_16_align3:
         subs r3, r3, #1
         add r0, r0, r2
         bne 1b
-        ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content.
+        ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
 
 @ ----------------------------------------------------------------
         .align
@@ -274,13 +274,13 @@ MC_put_x_16_align3:
 MC_put_x_8:
         @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
         @@ pld [r1]
-        stmfd sp!, {r4-r6, HIGH_REGS, lr} @ R14 is also called LR
-        and r4, r1, #3
+        stmfd sp!, {r6-HIGHEST_REG, lr} @ R14 is also called LR
+        and r6, r1, #3
         ldr r12, 2f
 #if ARM_ARCH < 6
         mvn r11, r12
 #endif
-        ldr pc, [pc, r4, lsl #2]
+        ldr pc, [pc, r6, lsl #2]
 2:      .word 0x01010101
         .word MC_put_x_8_align0
         .word MC_put_x_8_align1
@@ -288,55 +288,55 @@ MC_put_x_8:
         .word MC_put_x_8_align3
 
 MC_put_x_8_align0:
-        ldmia r1, {r4-r6}
+        ldmia r1, {r6-r8}
         add r1, r1, r2
         @@ pld [r1]
-        AVG_PW r5, r6
-        AVG_PW r4, r5
-        stmia r0, {r5-r6}
+        AVG_PW r7, r8
+        AVG_PW r6, r7
+        stmia r0, {r7-r8}
         subs r3, r3, #1
         add r0, r0, r2
         bne MC_put_x_8_align0
-        ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content.
+        ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
 
 MC_put_x_8_align1:
         and r1, r1, #0xFFFFFFFC
-1:      ldmia r1, {r4-r6}
+1:      ldmia r1, {r6-r8}
         add r1, r1, r2
         @@ pld [r1]
-        ADJ_ALIGN_DW 8, r4, r5, r6
-        AVG_PW r5, r6
-        AVG_PW r4, r5
-        stmia r0, {r5-r6}
+        ADJ_ALIGN_DW 8, r6, r7, r8
+        AVG_PW r7, r8
+        AVG_PW r6, r7
+        stmia r0, {r7-r8}
         subs r3, r3, #1
         add r0, r0, r2
         bne 1b
-        ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content.
+        ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
 
 MC_put_x_8_align2:
         and r1, r1, #0xFFFFFFFC
-1:      ldmia r1, {r4-r6}
+1:      ldmia r1, {r6-r8}
         add r1, r1, r2
         @@ pld [r1]
-        ADJ_ALIGN_DW 16, r4, r5, r6
-        AVG_PW r5, r6
-        AVG_PW r4, r5
-        stmia r0, {r5-r6}
+        ADJ_ALIGN_DW 16, r6, r7, r8
+        AVG_PW r7, r8
+        AVG_PW r6, r7
+        stmia r0, {r7-r8}
         subs r3, r3, #1
         add r0, r0, r2
         bne 1b
-        ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content.
+        ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
 
 MC_put_x_8_align3:
         and r1, r1, #0xFFFFFFFC
-1:      ldmia r1, {r4-r6}
+1:      ldmia r1, {r6-r8}
         add r1, r1, r2
         @@ pld [r1]
-        ADJ_ALIGN_DW 24, r4, r5, r6
-        AVG_PW r5, r6
-        AVG_PW r4, r5
-        stmia r0, {r5-r6}
+        ADJ_ALIGN_DW 24, r6, r7, r8
+        AVG_PW r7, r8
+        AVG_PW r6, r7
+        stmia r0, {r7-r8}
         subs r3, r3, #1
         add r0, r0, r2
         bne 1b
-        ldmpc regs="r4-r6, HIGH_REGS @@ update PC with LR content.
+        ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.