diff options
author | Rafaël Carré <rafael.carre@gmail.com> | 2010-06-11 04:41:36 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-06-11 04:41:36 +0000 |
commit | 45c7498f59ad2889f2120a865a51043004eddd5d (patch) | |
tree | 1a62b0e8549a7f2750679de8d7dd3f82039c5719 /apps/plugins | |
parent | fe7ca44471b309a0adea563cce947de9efb62ab5 (diff) | |
download | rockbox-45c7498f59ad2889f2120a865a51043004eddd5d.tar.gz rockbox-45c7498f59ad2889f2120a865a51043004eddd5d.zip |
FS#11335 by me: make ARM assembly functions thumb-friendly
We can't pop into pc on ARMv4t when using thumb: the T bit won't be
modified if we are returning to a thumb function
Code running on ARMv4t should use the new ldrpc / ldmpc macros instead
of ldr pc, [sp], #4 and ldm(cond) sp!, {regs, pc}
No modification on pure ARM builds and ARMv5+
Note: USE_THUMB is currently never defined, no targets can currently be
built with -mthumb, see FS#6734
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26756 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'apps/plugins')
-rw-r--r-- | apps/plugins/mpegplayer/idct_arm.S | 8 | ||||
-rw-r--r-- | apps/plugins/mpegplayer/motion_comp_arm_s.S | 32 | ||||
-rw-r--r-- | apps/plugins/pacbox/pacbox_arm.S | 3 |
3 files changed, 23 insertions, 20 deletions
diff --git a/apps/plugins/mpegplayer/idct_arm.S b/apps/plugins/mpegplayer/idct_arm.S index 7253d890bf..97a87a8b59 100644 --- a/apps/plugins/mpegplayer/idct_arm.S +++ b/apps/plugins/mpegplayer/idct_arm.S | |||
@@ -19,6 +19,8 @@ | |||
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | ||
23 | |||
22 | .global mpeg2_idct_copy | 24 | .global mpeg2_idct_copy |
23 | .type mpeg2_idct_copy, %function | 25 | .type mpeg2_idct_copy, %function |
24 | .global mpeg2_idct_add | 26 | .global mpeg2_idct_add |
@@ -313,7 +315,7 @@ mpeg2_idct_copy: | |||
313 | add r1, r1, r2 | 315 | add r1, r1, r2 |
314 | cmp r0, r12 | 316 | cmp r0, r12 |
315 | blo 1b | 317 | blo 1b |
316 | ldmfd sp!, { r4-r11, pc } | 318 | ldmpc regs=r4-r11 |
317 | 319 | ||
318 | mpeg2_idct_add: | 320 | mpeg2_idct_add: |
319 | cmp r0, #129 | 321 | cmp r0, #129 |
@@ -385,7 +387,7 @@ mpeg2_idct_add: | |||
385 | add r1, r1, r2 | 387 | add r1, r1, r2 |
386 | cmp r0, r12 | 388 | cmp r0, r12 |
387 | blo 2b | 389 | blo 2b |
388 | ldmfd sp!, { r4-r11, pc } | 390 | ldmpc regs=r4-r11 |
389 | 3: | 391 | 3: |
390 | stmfd sp!, { r4-r5, lr } | 392 | stmfd sp!, { r4-r5, lr } |
391 | ldrsh r1, [r0, #0] /* r1 = block[0] */ | 393 | ldrsh r1, [r0, #0] /* r1 = block[0] */ |
@@ -438,4 +440,4 @@ mpeg2_idct_add: | |||
438 | add r2, r2, r3 | 440 | add r2, r2, r3 |
439 | cmp r2, r0 | 441 | cmp r2, r0 |
440 | blo 4b | 442 | blo 4b |
441 | ldmfd sp!, { r4-r5, pc } | 443 | ldmpc regs=r4-r5 |
diff --git a/apps/plugins/mpegplayer/motion_comp_arm_s.S b/apps/plugins/mpegplayer/motion_comp_arm_s.S index fb29d59e99..49628c6ad5 100644 --- a/apps/plugins/mpegplayer/motion_comp_arm_s.S +++ b/apps/plugins/mpegplayer/motion_comp_arm_s.S | |||
@@ -47,7 +47,7 @@ MC_put_o_16_align0: | |||
47 | subs r3, r3, #1 | 47 | subs r3, r3, #1 |
48 | add r0, r0, r2 | 48 | add r0, r0, r2 |
49 | bne MC_put_o_16_align0 | 49 | bne MC_put_o_16_align0 |
50 | ldmfd sp!, {r4-r7, pc} @@ update PC with LR content. | 50 | ldmpc regs=r4-r7 @@ update PC with LR content. |
51 | 51 | ||
52 | .macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4 | 52 | .macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4 |
53 | mov \R0, \R0, lsr #(\shift) | 53 | mov \R0, \R0, lsr #(\shift) |
@@ -71,7 +71,7 @@ MC_put_o_16_align1: | |||
71 | subs r3, r3, #1 | 71 | subs r3, r3, #1 |
72 | add r0, r0, r2 | 72 | add r0, r0, r2 |
73 | bne 1b | 73 | bne 1b |
74 | ldmfd sp!, {r4-r7, pc} @@ update PC with LR content. | 74 | ldmpc regs=r4-r7 @@ update PC with LR content. |
75 | 75 | ||
76 | MC_put_o_16_align2: | 76 | MC_put_o_16_align2: |
77 | and r1, r1, #0xFFFFFFFC | 77 | and r1, r1, #0xFFFFFFFC |
@@ -83,7 +83,7 @@ MC_put_o_16_align2: | |||
83 | subs r3, r3, #1 | 83 | subs r3, r3, #1 |
84 | add r0, r0, r2 | 84 | add r0, r0, r2 |
85 | bne 1b | 85 | bne 1b |
86 | ldmfd sp!, {r4-r7, pc} @@ update PC with LR content. | 86 | ldmpc regs=r4-r7 @@ update PC with LR content. |
87 | 87 | ||
88 | MC_put_o_16_align3: | 88 | MC_put_o_16_align3: |
89 | and r1, r1, #0xFFFFFFFC | 89 | and r1, r1, #0xFFFFFFFC |
@@ -95,7 +95,7 @@ MC_put_o_16_align3: | |||
95 | subs r3, r3, #1 | 95 | subs r3, r3, #1 |
96 | add r0, r0, r2 | 96 | add r0, r0, r2 |
97 | bne 1b | 97 | bne 1b |
98 | ldmfd sp!, {r4-r7, pc} @@ update PC with LR content. | 98 | ldmpc regs=r4-r7 @@ update PC with LR content. |
99 | 99 | ||
100 | @ ---------------------------------------------------------------- | 100 | @ ---------------------------------------------------------------- |
101 | .align | 101 | .align |
@@ -120,7 +120,7 @@ MC_put_o_8_align0: | |||
120 | add r0, r0, r2 | 120 | add r0, r0, r2 |
121 | subs r3, r3, #1 | 121 | subs r3, r3, #1 |
122 | bne MC_put_o_8_align0 | 122 | bne MC_put_o_8_align0 |
123 | ldmfd sp!, {r4, r5, pc} @@ update PC with LR content. | 123 | ldmpc regs=r4-r5 @@ update PC with LR content. |
124 | 124 | ||
125 | .macro ADJ_ALIGN_DW shift, R0, R1, R2 | 125 | .macro ADJ_ALIGN_DW shift, R0, R1, R2 |
126 | mov \R0, \R0, lsr #(\shift) | 126 | mov \R0, \R0, lsr #(\shift) |
@@ -140,7 +140,7 @@ MC_put_o_8_align1: | |||
140 | subs r3, r3, #1 | 140 | subs r3, r3, #1 |
141 | add r0, r0, r2 | 141 | add r0, r0, r2 |
142 | bne 1b | 142 | bne 1b |
143 | ldmfd sp!, {r4, r5, pc} @@ update PC with LR content. | 143 | ldmpc regs=r4-r5 @@ update PC with LR content. |
144 | 144 | ||
145 | MC_put_o_8_align2: | 145 | MC_put_o_8_align2: |
146 | and r1, r1, #0xFFFFFFFC | 146 | and r1, r1, #0xFFFFFFFC |
@@ -152,7 +152,7 @@ MC_put_o_8_align2: | |||
152 | subs r3, r3, #1 | 152 | subs r3, r3, #1 |
153 | add r0, r0, r2 | 153 | add r0, r0, r2 |
154 | bne 1b | 154 | bne 1b |
155 | ldmfd sp!, {r4, r5, pc} @@ update PC with LR content. | 155 | ldmpc regs=r4-r5 @@ update PC with LR content. |
156 | 156 | ||
157 | MC_put_o_8_align3: | 157 | MC_put_o_8_align3: |
158 | and r1, r1, #0xFFFFFFFC | 158 | and r1, r1, #0xFFFFFFFC |
@@ -164,7 +164,7 @@ MC_put_o_8_align3: | |||
164 | subs r3, r3, #1 | 164 | subs r3, r3, #1 |
165 | add r0, r0, r2 | 165 | add r0, r0, r2 |
166 | bne 1b | 166 | bne 1b |
167 | ldmfd sp!, {r4, r5, pc} @@ update PC with LR content. | 167 | ldmpc regs=r4-r5 @@ update PC with LR content. |
168 | 168 | ||
169 | @ ---------------------------------------------------------------- | 169 | @ ---------------------------------------------------------------- |
170 | .macro AVG_PW rW1, rW2 | 170 | .macro AVG_PW rW1, rW2 |
@@ -218,7 +218,7 @@ MC_put_x_16_align0: | |||
218 | subs r3, r3, #1 | 218 | subs r3, r3, #1 |
219 | add r0, r0, r2 | 219 | add r0, r0, r2 |
220 | bne MC_put_x_16_align0 | 220 | bne MC_put_x_16_align0 |
221 | ldmfd sp!, {r4-r8, HIGH_REGS, pc} @@ update PC with LR content. | 221 | ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. |
222 | 222 | ||
223 | MC_put_x_16_align1: | 223 | MC_put_x_16_align1: |
224 | and r1, r1, #0xFFFFFFFC | 224 | and r1, r1, #0xFFFFFFFC |
@@ -234,7 +234,7 @@ MC_put_x_16_align1: | |||
234 | subs r3, r3, #1 | 234 | subs r3, r3, #1 |
235 | add r0, r0, r2 | 235 | add r0, r0, r2 |
236 | bne 1b | 236 | bne 1b |
237 | ldmfd sp!, {r4-r8, HIGH_REGS, pc} @@ update PC with LR content. | 237 | ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. |
238 | 238 | ||
239 | MC_put_x_16_align2: | 239 | MC_put_x_16_align2: |
240 | and r1, r1, #0xFFFFFFFC | 240 | and r1, r1, #0xFFFFFFFC |
@@ -250,7 +250,7 @@ MC_put_x_16_align2: | |||
250 | subs r3, r3, #1 | 250 | subs r3, r3, #1 |
251 | add r0, r0, r2 | 251 | add r0, r0, r2 |
252 | bne 1b | 252 | bne 1b |
253 | ldmfd sp!, {r4-r8, HIGH_REGS, pc} @@ update PC with LR content. | 253 | ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. |
254 | 254 | ||
255 | MC_put_x_16_align3: | 255 | MC_put_x_16_align3: |
256 | and r1, r1, #0xFFFFFFFC | 256 | and r1, r1, #0xFFFFFFFC |
@@ -266,7 +266,7 @@ MC_put_x_16_align3: | |||
266 | subs r3, r3, #1 | 266 | subs r3, r3, #1 |
267 | add r0, r0, r2 | 267 | add r0, r0, r2 |
268 | bne 1b | 268 | bne 1b |
269 | ldmfd sp!, {r4-r8, HIGH_REGS, pc} @@ update PC with LR content. | 269 | ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. |
270 | 270 | ||
271 | @ ---------------------------------------------------------------- | 271 | @ ---------------------------------------------------------------- |
272 | .align | 272 | .align |
@@ -297,7 +297,7 @@ MC_put_x_8_align0: | |||
297 | subs r3, r3, #1 | 297 | subs r3, r3, #1 |
298 | add r0, r0, r2 | 298 | add r0, r0, r2 |
299 | bne MC_put_x_8_align0 | 299 | bne MC_put_x_8_align0 |
300 | ldmfd sp!, {r4-r6, HIGH_REGS, pc} @@ update PC with LR content. | 300 | ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. |
301 | 301 | ||
302 | MC_put_x_8_align1: | 302 | MC_put_x_8_align1: |
303 | and r1, r1, #0xFFFFFFFC | 303 | and r1, r1, #0xFFFFFFFC |
@@ -311,7 +311,7 @@ MC_put_x_8_align1: | |||
311 | subs r3, r3, #1 | 311 | subs r3, r3, #1 |
312 | add r0, r0, r2 | 312 | add r0, r0, r2 |
313 | bne 1b | 313 | bne 1b |
314 | ldmfd sp!, {r4-r6, HIGH_REGS, pc} @@ update PC with LR content. | 314 | ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. |
315 | 315 | ||
316 | MC_put_x_8_align2: | 316 | MC_put_x_8_align2: |
317 | and r1, r1, #0xFFFFFFFC | 317 | and r1, r1, #0xFFFFFFFC |
@@ -325,7 +325,7 @@ MC_put_x_8_align2: | |||
325 | subs r3, r3, #1 | 325 | subs r3, r3, #1 |
326 | add r0, r0, r2 | 326 | add r0, r0, r2 |
327 | bne 1b | 327 | bne 1b |
328 | ldmfd sp!, {r4-r6, HIGH_REGS, pc} @@ update PC with LR content. | 328 | ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. |
329 | 329 | ||
330 | MC_put_x_8_align3: | 330 | MC_put_x_8_align3: |
331 | and r1, r1, #0xFFFFFFFC | 331 | and r1, r1, #0xFFFFFFFC |
@@ -339,4 +339,4 @@ MC_put_x_8_align3: | |||
339 | subs r3, r3, #1 | 339 | subs r3, r3, #1 |
340 | add r0, r0, r2 | 340 | add r0, r0, r2 |
341 | bne 1b | 341 | bne 1b |
342 | ldmfd sp!, {r4-r6, HIGH_REGS, pc} @@ update PC with LR content. | 342 | ldmpc regs="r4-r6, HIGH_REGS @@ update PC with LR content. |
diff --git a/apps/plugins/pacbox/pacbox_arm.S b/apps/plugins/pacbox/pacbox_arm.S index 32cf2d447e..87696ce6f7 100644 --- a/apps/plugins/pacbox/pacbox_arm.S +++ b/apps/plugins/pacbox/pacbox_arm.S | |||
@@ -19,6 +19,7 @@ | |||
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | ||
22 | #include "pacbox.h" | 23 | #include "pacbox.h" |
23 | 24 | ||
24 | .section .icode,"ax",%progbits | 25 | .section .icode,"ax",%progbits |
@@ -120,7 +121,7 @@ loop_x: | |||
120 | /* end of y loop */ | 121 | /* end of y loop */ |
121 | add r1, r1, #224*3 @ vbuf += 224*3 | 122 | add r1, r1, #224*3 @ vbuf += 224*3 |
122 | subs lr, lr, #4 @ y-=4 | 123 | subs lr, lr, #4 @ y-=4 |
123 | ldmeqia sp!, {r4-r11, pc} | 124 | ldmpc cond=eq, regs=r4-r11 |
124 | b loop_y | 125 | b loop_y |
125 | #endif | 126 | #endif |
126 | #endif | 127 | #endif |