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author | Jens Arnold <amiconn@rockbox.org> | 2007-07-10 20:47:01 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2007-07-10 20:47:01 +0000 |
commit | 85568d6040935af76f62d76ac9a106c6fb7c754b (patch) | |
tree | f8bc2e7bf7b51cf815ea3e10eaf7854808a0c529 /apps/debug_menu.c | |
parent | 696432a2fdc55407651d0cdc257549a458a0dc0e (diff) | |
download | rockbox-85568d6040935af76f62d76ac9a106c6fb7c754b.tar.gz rockbox-85568d6040935af76f62d76ac9a106c6fb7c754b.zip |
iPod G3: Clock setup register display and CPU clock estimation in debug menu. * Fix clock being set to only half of what it should be (introduced with clock setup changes for PP502x).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13844 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'apps/debug_menu.c')
-rw-r--r-- | apps/debug_menu.c | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/apps/debug_menu.c b/apps/debug_menu.c index 691bbf9cd9..eff8def487 100644 --- a/apps/debug_menu.c +++ b/apps/debug_menu.c | |||
@@ -405,7 +405,7 @@ static bool dbg_flash_id(unsigned* p_manufacturer, unsigned* p_device, | |||
405 | #endif /* (CONFIG_CPU == SH7034 || CPU_COLDFIRE) */ | 405 | #endif /* (CONFIG_CPU == SH7034 || CPU_COLDFIRE) */ |
406 | 406 | ||
407 | #ifndef SIMULATOR | 407 | #ifndef SIMULATOR |
408 | #ifdef CPU_PP502x | 408 | #ifdef CPU_PP |
409 | static int perfcheck(void) | 409 | static int perfcheck(void) |
410 | { | 410 | { |
411 | int result; | 411 | int result; |
@@ -427,7 +427,13 @@ static int perfcheck(void) | |||
427 | [res]"=&r"(result) | 427 | [res]"=&r"(result) |
428 | : | 428 | : |
429 | [timr]"r"(&USEC_TIMER), | 429 | [timr]"r"(&USEC_TIMER), |
430 | [tmo]"r"(10226) | 430 | [tmo]"r"( |
431 | #if CONFIG_CPU == PP5002 | ||
432 | 16000 | ||
433 | #else /* PP5020/5022/5024 */ | ||
434 | 10226 | ||
435 | #endif | ||
436 | ) | ||
431 | : | 437 | : |
432 | "r0", "r1", "r2" | 438 | "r0", "r1", "r2" |
433 | ); | 439 | ); |
@@ -586,7 +592,7 @@ static bool dbg_hw_info(void) | |||
586 | 592 | ||
587 | snprintf(buf, sizeof(buf), "Est. clock (kHz): %d", perfcheck()); | 593 | snprintf(buf, sizeof(buf), "Est. clock (kHz): %d", perfcheck()); |
588 | lcd_puts(0, 3, buf); | 594 | lcd_puts(0, 3, buf); |
589 | 595 | ||
590 | lcd_update(); | 596 | lcd_update(); |
591 | 597 | ||
592 | while(1) | 598 | while(1) |
@@ -1181,6 +1187,23 @@ bool dbg_ports(void) | |||
1181 | snprintf(buf, sizeof(buf), "GPIO_C: %02x GPIO_D: %02x", gpio_c, gpio_d); | 1187 | snprintf(buf, sizeof(buf), "GPIO_C: %02x GPIO_D: %02x", gpio_c, gpio_d); |
1182 | lcd_puts(0, line++, buf); | 1188 | lcd_puts(0, line++, buf); |
1183 | 1189 | ||
1190 | snprintf(buf, sizeof(buf), "CLOCK_ENABLE: %08lx", CLOCK_ENABLE); | ||
1191 | lcd_puts(0, line++, buf); | ||
1192 | snprintf(buf, sizeof(buf), "CLOCK_SOURCE: %08lx", CLOCK_SOURCE); | ||
1193 | lcd_puts(0, line++, buf); | ||
1194 | snprintf(buf, sizeof(buf), "CLOCK_DIV: %08lx", CLOCK_DIV); | ||
1195 | lcd_puts(0, line++, buf); | ||
1196 | snprintf(buf, sizeof(buf), "PLL_DIV: %08lx", PLL_DIV); | ||
1197 | lcd_puts(0, line++, buf); | ||
1198 | snprintf(buf, sizeof(buf), "PLL_MULT: %08lx", PLL_MULT); | ||
1199 | lcd_puts(0, line++, buf); | ||
1200 | snprintf(buf, sizeof(buf), "TIMING1_CTL: %08lx", TIMING1_CTL); | ||
1201 | lcd_puts(0, line++, buf); | ||
1202 | snprintf(buf, sizeof(buf), "TIMING2_CTL: %08lx", TIMING2_CTL); | ||
1203 | lcd_puts(0, line++, buf); | ||
1204 | snprintf(buf, sizeof(buf), "Est. clock (kHz): %d", perfcheck()); | ||
1205 | lcd_puts(0, line++, buf); | ||
1206 | |||
1184 | lcd_update(); | 1207 | lcd_update(); |
1185 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) | 1208 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) |
1186 | return false; | 1209 | return false; |