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authorMichael Sevakis <jethead71@rockbox.org>2007-07-17 00:23:56 +0000
committerMichael Sevakis <jethead71@rockbox.org>2007-07-17 00:23:56 +0000
commitfb102bab70c92ba9f2a2b88438164b704547601c (patch)
tree2cc110aa7e9df9283b42e7e8bf3f1648e3d20452
parent8219912d918e8c060bfbebb8c0e4041852db6944 (diff)
downloadrockbox-fb102bab70c92ba9f2a2b88438164b704547601c.tar.gz
rockbox-fb102bab70c92ba9f2a2b88438164b704547601c.zip
Fix my mistakes in some bits in the WM8751 header. Looks like adaptive boost has been turned on by mistake anyway. Correct that and make sure it is turned on intentionally with the #define. Organize a little bit in there.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13923 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/export/wm8751.h67
1 files changed, 32 insertions, 35 deletions
diff --git a/firmware/export/wm8751.h b/firmware/export/wm8751.h
index 782027433a..23966fd568 100644
--- a/firmware/export/wm8751.h
+++ b/firmware/export/wm8751.h
@@ -78,17 +78,6 @@ extern void audiohw_set_frequency(int fsel);
78 78
79#define CLOCKING 0x08 79#define CLOCKING 0x08
80#define CLOCKING_SR_USB (1 << 0) 80#define CLOCKING_SR_USB (1 << 0)
81/* Register settings for the supported samplerates: */
82#define WM8975_8000HZ 0x4d
83#define WM8975_12000HZ 0x61
84#define WM8975_16000HZ 0x55
85#define WM8975_22050HZ 0x77
86#define WM8975_24000HZ 0x79
87#define WM8975_32000HZ 0x59
88#define WM8975_44100HZ 0x63
89#define WM8975_48000HZ 0x41
90#define WM8975_88200HZ 0x7f
91#define WM8975_96000HZ 0x5d
92#define CLOCKING_SR(x) ((x) & (0x1f << 1)) 81#define CLOCKING_SR(x) ((x) & (0x1f << 1))
93#define CLOCKING_MCLK_DIV2 (1 << 6) 82#define CLOCKING_MCLK_DIV2 (1 << 6)
94#define CLOCKING_BCLK_DIV2 (1 << 7) 83#define CLOCKING_BCLK_DIV2 (1 << 7)
@@ -103,12 +92,12 @@ extern void audiohw_set_frequency(int fsel);
103 92
104#define BASSCTRL 0x0c 93#define BASSCTRL 0x0c
105#define BASSCTRL_BASS(x) ((x) & 0xf) 94#define BASSCTRL_BASS(x) ((x) & 0xf)
106#define BASSCTRL_BC (1 << 7) 95#define BASSCTRL_BC (1 << 6)
107#define BASSCTRL_BB (1 << 8) 96#define BASSCTRL_BB (1 << 7)
108 97
109#define TREBCTRL 0x0d 98#define TREBCTRL 0x0d
110#define TREBCTRL_TREB(x) ((x) & 0xf) 99#define TREBCTRL_TREB(x) ((x) & 0xf)
111#define TREBCTRL_TC (1 << 7) 100#define TREBCTRL_TC (1 << 6)
112 101
113#define RESET 0x0f 102#define RESET 0x0f
114#define RESET_RESET 0x000 103#define RESET_RESET 0x000
@@ -126,11 +115,19 @@ extern void audiohw_set_frequency(int fsel);
126#define ADDITIONAL1_VSEL_DEFAULT2 (2 << 6) 115#define ADDITIONAL1_VSEL_DEFAULT2 (2 << 6)
127#define ADDITIONAL1_VSEL_DEFAULT (3 << 6) 116#define ADDITIONAL1_VSEL_DEFAULT (3 << 6)
128#define ADDITIONAL1_VSEL(x) ((x) & (0x3 << 6)) 117#define ADDITIONAL1_VSEL(x) ((x) & (0x3 << 6))
129#define ADDITIONAL1_TSDEN (1 << 7) 118#define ADDITIONAL1_TSDEN (1 << 8)
130 119
131#define ADDITIONAL2 0x18 120#define ADDITIONAL2 0x18
132#define ADDITIONAL2_ROUT2INV (1 << 4)
133#define ADDITIONAL2_DACOSR (1 << 0) 121#define ADDITIONAL2_DACOSR (1 << 0)
122#define ADDITIONAL2_HPSWZC (1 << 3)
123#define ADDITIONAL2_ROUT2INV (1 << 4)
124#define ADDITIONAL2_HPSWPOL (1 << 5)
125#define ADDITIONAL2_HPSWEN (1 << 6)
126#define ADDITIONAL2_OUT3SW_VREF (0 << 7)
127#define ADDITIONAL2_OUT3SW_ROUT1 (1 << 7)
128#define ADDITIONAL2_OUT3SW_MONOOUT (2 << 7)
129#define ADDITIONAL2_OUT3SW_R_MIX_OUT (3 << 7)
130#define ADDITIONAL2_OUT3SW(x) ((x) & (0x3 << 7))
134 131
135#define PWRMGMT1 0x19 132#define PWRMGMT1 0x19
136#define PWRMGMT1_DIGENB (1 << 0) 133#define PWRMGMT1_DIGENB (1 << 0)
@@ -142,54 +139,54 @@ extern void audiohw_set_frequency(int fsel);
142#define PWRMGMT1_VMIDSEL(x) ((x) & (0x3 << 7)) 139#define PWRMGMT1_VMIDSEL(x) ((x) & (0x3 << 7))
143 140
144#define PWRMGMT2 0x1a 141#define PWRMGMT2 0x1a
145#define PWRMGMT2_DACL (1 << 8)
146#define PWRMGMT2_DACR (1 << 7)
147#define PWRMGMT2_LOUT1 (1 << 6)
148#define PWRMGMT2_ROUT1 (1 << 5)
149#define PWRMGMT2_LOUT2 (1 << 4)
150#define PWRMGMT2_ROUT2 (1 << 3)
151#define PWRMGMT2_MOUT (1 << 2)
152#define PWRMGMT2_OUT3 (1 << 1) 142#define PWRMGMT2_OUT3 (1 << 1)
143#define PWRMGMT2_MOUT (1 << 2)
144#define PWRMGMT2_ROUT2 (1 << 3)
145#define PWRMGMT2_LOUT2 (1 << 4)
146#define PWRMGMT2_ROUT1 (1 << 5)
147#define PWRMGMT2_LOUT1 (1 << 6)
148#define PWRMGMT2_DACR (1 << 7)
149#define PWRMGMT2_DACL (1 << 8)
153 150
154#define ADDITIONAL3 0x1b 151#define ADDITIONAL3 0x1b
155#define ADDITIONAL3_ADCLRM ((x) & (0x3 << 7)) 152#define ADDITIONAL3_ADCLRM ((x) & (0x3 << 7))
156#define ADDITIONAL3_VROI (1 << 6)
157#define ADDITIONAL3_HPFLREN (1 << 5) 153#define ADDITIONAL3_HPFLREN (1 << 5)
154#define ADDITIONAL3_VROI (1 << 6)
158 155
159#define LEFTMIX1 0x22 156#define LEFTMIX1 0x22
160#define LEFTMIX1_LD2LO (1 << 8)
161#define LEFTMIX1_LI2LO (1 << 7)
162#define LEFTMIX1_LI2LO_DEFAULT (5 << 4) 157#define LEFTMIX1_LI2LO_DEFAULT (5 << 4)
163#define LEFTMIX1_LI2LOVOL(x) ((x) & (0x7 << 4)) 158#define LEFTMIX1_LI2LOVOL(x) ((x) & (0x7 << 4))
159#define LEFTMIX1_LI2LO (1 << 7)
160#define LEFTMIX1_LD2LO (1 << 8)
164 161
165#define LEFTMIX2 0x23 162#define LEFTMIX2 0x23
166#define LEFTMIX2_RD2LO (1 << 8)
167#define LEFTMIX2_MI2LO (1 << 7)
168#define LEFTMIX2_MI2LO_DEFAULT (5 << 4) 163#define LEFTMIX2_MI2LO_DEFAULT (5 << 4)
169#define LEFTMIX2_MI2LOVOL(x) ((x) & (0x7 << 4)) 164#define LEFTMIX2_MI2LOVOL(x) ((x) & (0x7 << 4))
165#define LEFTMIX2_MI2LO (1 << 7)
166#define LEFTMIX2_RD2LO (1 << 8)
170 167
171#define RIGHTMIX1 0x24 168#define RIGHTMIX1 0x24
172#define RIGHTMIX1_LD2RO (1 << 8)
173#define RIGHTMIX1_MI2RO (1 << 7)
174#define RIGHTMIX1_MI2RO_DEFAULT (5 << 4) 169#define RIGHTMIX1_MI2RO_DEFAULT (5 << 4)
175#define RIGHTMIX1_MI2ROVOL(x) ((x) & (0x7 << 4)) 170#define RIGHTMIX1_MI2ROVOL(x) ((x) & (0x7 << 4))
171#define RIGHTMIX1_MI2RO (1 << 7)
172#define RIGHTMIX1_LD2RO (1 << 8)
176 173
177#define RIGHTMIX2 0x25 174#define RIGHTMIX2 0x25
178#define RIGHTMIX2_RD2RO (1 << 8)
179#define RIGHTMIX2_RI2RO (1 << 7)
180#define RIGHTMIX2_RI2RO_DEFAULT (5 << 4) 175#define RIGHTMIX2_RI2RO_DEFAULT (5 << 4)
181#define RIGHTMIX2_RI2ROVOL(x) ((x) & (0x7 << 4)) 176#define RIGHTMIX2_RI2ROVOL(x) ((x) & (0x7 << 4))
177#define RIGHTMIX2_RI2RO (1 << 7)
178#define RIGHTMIX2_RD2RO (1 << 8)
182 179
183#define MONOMIX1 0x26 180#define MONOMIX1 0x26
181#define MONOMIX1_DMEN (1 << 0)
184#define MONOMIX1_LI2MOVOL(x) ((x) & (0x7 << 4)) 182#define MONOMIX1_LI2MOVOL(x) ((x) & (0x7 << 4))
185#define MONOMIX1_LI2MO (1 << 7) 183#define MONOMIX1_LI2MO (1 << 7)
186#define MONOMIX1_LD2MO (1 << 8) 184#define MONOMIX1_LD2MO (1 << 8)
187#define MONOMIX1_DMEN (1 << 0)
188 185
189#define MONOMIX2 0x27 186#define MONOMIX2 0x27
190#define MONOMIX2_RD2MO (1 << 8)
191#define MONOMIX2_RI2MO (1 << 7)
192#define MONOMIX2_RI2MOVOL(x) ((x) & (0x7 << 4)) 187#define MONOMIX2_RI2MOVOL(x) ((x) & (0x7 << 4))
188#define MONOMIX2_RI2MO (1 << 7)
189#define MONOMIX2_RD2MO (1 << 8)
193 190
194#define LOUT2 0x28 191#define LOUT2 0x28
195#define LOUT2_LOUT2VOL(x) ((x) & 0x7f) 192#define LOUT2_LOUT2VOL(x) ((x) & 0x7f)